SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 166

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Synchronous Serial Interface (ESSI)
7.6.2 Port Direction Registers (PRRC and PRRD)
The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO signals
when they are enabled by the associated Port Control Register (PCRC or PCRD, respectively).
When PRRC[i] or PRRD[i] is set, the corresponding signal is an output (GPO) signal. When
PRRC[i] or PRRD[i] is cleared, the corresponding signal is an input (GPI) signal. Either a
hardware
Table 7-6 summarizes the ESSI port signal configurations.
7.6.3 Port Data Registers (PDRC and PDRD)
Bits 5–0 of the read/write PDRs write data to or read data from the associated ESSI GPIO signal
lines if they are configured as GPIO signals. If a port signal PC[i] or PD[i] is configured as an
input (GPI), the corresponding PDRC[i] pr PDRD[i] bit reflects the value present on the input
7-34
Note:
Note:
X: The signal setting is irrelevant to the Port Signal[i] function.
23
11
23
11
PCRC/PCRD[i]
For Px[5–0], a 0 selects Pxn as the signal and a 1 selects the specified ESSI signal. For ESSI0, the GPIO signals are
PC[5–0] and the ESSI signals are STD0, SRD0, SCK0, and SC0[2–0]. For ESSI1, the GPIO signals are PD[5–0] and
the ESSI signals are STD1, SRD1, SCK1, and SC1[2–0].
For bits 5–0, a 0 configures PRxn as a GPI and a 1 configures PRxn as a GPO. For ESSI0, the GPIO signals are
PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding direction bits for Port C GPIOs are PRC[5–0].
The corresponding direction bits for Port D GPIOs are PRD[5–0].
Figure 7-19. Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE)
= Reserved. Read as zero. Write with zero for future compatibility.
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-18. Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF)
RESET
1
0
0
22
10
22
10
signal or a software RESET instruction clears all PRRC and PRRD bits.
21
21
9
9
PRRC/PRRD[i]
Table 7-6. ESSI Port Signal Configurations
20
20
8
8
X
0
1
DSP56303 User’s Manual, Rev. 2
19
19
7
7
18
18
6
6
PCx5
PRx5
17
17
5
5
PCx4
PRx4
16
16
4
4
Port Signal[i] Function
Port C/Port D GPO
Port C/Port D GPI
ESSI0/ESSI1
PCx3
PRx3
15
15
3
3
PRx2
PCx2
14
14
2
2
Freescale Semiconductor
PRx1
PCx1
13
13
1
1
PRx0
PCx0
12
12
0
0