SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 36

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
2-12
HCS
HA10
PB13
HREQ
HTRQ
PB14
HACK
HRRQ
PB15
Notes: 1.
Signal Name
/HTRQ
/HACK
/HREQ
/HRRQ
2.
In the Stop state, the signal maintains the last state as follows:
•
•
The Wait processing state does not affect the signal state.
If the last state is input, the signal is an ignored input.
If the last state is output, these lines are tri-stated
Input or
Input or
Input or
Output
Output
Output
Output
Output
Output
Type
Input
Input
Input
State During
Ignored input
Ignored input
Ignored input
Table 2-11. Host Interface (Continued)
Reset
1,2
DSP56303 User’s Manual, Rev. 2
Host Chip Select
When the HI08 is programmed to interface with a non-multiplexed host
bus and the HI function is selected, this signal is the Host Chip Select
(HCS) input. The polarity of the chip select is programmable, but is
configured active-low (HCS) after reset.
Host Address 10
When the HI08 is programmed to interface with a multiplexed host bus
and the HI function is selected, this signal is line 10 of the Host Address
bus.
Port B 13
When the HI08 is configured as GPIO through the HPCR, this signal is
individually programmed through the HDDR. This input is 5 V tolerant.
Host Request
When the HI08 is programmed to interface with a single host request host
bus and the HI function is selected, this signal is the Host Request
(HREQ) output. The polarity of the host request is programmable, but is
configured as active-low (HREQ) following reset. The host request can be
programmed as a driven or open-drain output.
Transmit Host Request
When the HI08 is programmed to interface with a double host request
host bus and the HI function is selected, this signal is the Transmit Host
Request (HTRQ) output. The polarity of the host request is
programmable, but is configured as active-low (HTRQ) following reset.
The host request may be programmed as a driven or open-drain output.
Port B 14
When the HI08 is configured as GPIO through the HPCR, this signal is
individually programmed through the HDDR. This input is 5 V tolerant.
Host Acknowledge
When the HI08 is programmed to interface with a single host request host
bus and the HI function is selected, this signal is the Host Acknowledge
(HACK) Schmitt-trigger input. The polarity of the host acknowledge is
programmable, but is configured as active-low (HACK) after reset.
Receive Host Request
When the HI08 is programmed to interface with a double host request
host bus and the HI function is selected, this signal is the Receive Host
Request (HRRQ) output. The polarity of the host request is
programmable, but is configured as active-low (HRRQ) after reset. The
host request may be programmed as a driven or open-drain output.
Port B 15
When the HI08 is configured as GPIO through the HPCR, this signal is
individually programmed through the HDDR. This input is 5 V tolerant.
Signal Description
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