SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 32

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
2-8
RESET
MODA/IRQA
MODB/IRQB
MODC/IRQC
Signal Name
Input
Input
Input
Input
Type
Input
Input
Input
Input
State During
Reset
Table 2-9. Interrupt and Mode Control
DSP56303 User’s Manual, Rev. 2
Reset
Deassertion of RESET is internally synchronized to the clock out
(CLKOUT). When asserted, the chip is placed in the Reset state and the
internal phase generator is reset. The Schmitt-trigger input allows a slowly
rising input (such as a capacitor charging) to reset the chip reliably. If
RESET is deasserted synchronous to CLKOUT, exact start-up timing is
guaranteed, allowing multiple processors to start and operate
synchronously. When the RESET signal is deasserted, the initial chip
operating mode is latched from the MODA, MODB, MODC, and MODD
inputs. The RESET signal must be asserted after power-up.
RESET can tolerate 5 V.
Mode Select A/External Interrupt Request A
Selects the initial chip operating mode during hardware reset and becomes
a level-sensitive or negative-edge-triggered, maskable interrupt request
input during normal instruction processing. MODA/IRQA MODA, MODB,
MODC, and MODD select one of sixteen initial chip operating modes,
latched into the OMR when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQA is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQA to exit the Wait state. If a STOP instruction
puts the processor is in the Stop standby state and IRQA is asserted, the
processor exits the Stop state.
MODA
Mode Select B/External Interrupt Request B
Selects the initial chip operating mode during hardware reset and becomes
a level-sensitive or negative-edge-triggered, maskable interrupt request
input during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into OMR
when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQB is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQB to exit the Wait state.
MODB/IRQB can tolerate 5 V.
Mode Select C/External Interrupt Request C
Selects the initial chip operating mode during hardware reset and becomes
a level-sensitive or negative-edge-triggered, maskable interrupt request
input during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into OMR
when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQC is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQC to exit the Wait state.
MODC/IRQC can tolerate 5 V.
/IRQA can tolerate 5 V.
Signal Description
Freescale Semiconductor