SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 165

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RSMA and RSMB (as in Figure 7-12 and Figure 7-13) can be seen as one 32-bit register, RSM.
Bit n in RSM (RSn) is an enable/disable control bit for time slot number N. When RSn is cleared,
all the data signals of the enabled receivers are tri-stated during time slot number N. Data
transfers from the receive data register(s) to the receive shift register(s), but the RDF and ROE
flags are not set. Consequently, during a disabled slot, no receiver full interrupt is generated. The
DSP is interrupted only for enabled slots. When RSn is set, the receive sequence proceeds
normally. Data is received during slot number N, and the RDF flag is set.
When the bits in the RSMx are set, the frame being transmitted is unaffected, but the next frame
transmission is affected. If the RSMx is read, it shows the current setting. When the internal data
bus reads RSMA or RSMB, the register contents occupy the two low-order bytes of the data bus,
and the high-order byte is filled by 0.
After a hardware
$FFFFFFFF, enabling all 32 time slots for data transmission.
7.6 GPIO Signals and Registers
The functionality of each ESSI port is controlled by three registers: port control register (PCRC,
PCRD), port direction register (PRRC, PRRD), and port data register (PDRC, PDRD).
7.6.1 Port Control Registers (PCRC and PCRD)
The read/write 24-bit PCRs control the functionality of the signal lines for ESSI0 and ESSI1.
Each of the PCR bits 5–0 controls the functionality of the corresponding signal line. When a
PCR[i] bit is set, the corresponding port signal is configured as an ESSI signal. When a PCR[i]
bit is cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware
RESET
Freescale Semiconductor
RS27
23
11
signal or a software RESET instruction clears all PCR bits.
–Reserved. Read as zero. Write with zero for future compatibility.
RS26
22
10
RESET
RS25
Figure 7-17. ESSI Receive Slot Mask Register B (RSMB)
21
9
signal or a software RESET instruction, the RSM register is reset to
RS24
20
8
(ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1)
RS23
DSP56303 User’s Manual, Rev. 2
19
7
RS22
18
6
RS21
17
5
RS20
16
4
RS31
RS19
15
3
GPIO Signals and Registers
RS30
RS18
14
2
RS29
RS17
13
1
RS28
RS16
12
0
7-33