SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 88

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Configuration
4-30
Number
18–17
Bit
Bit Name
DPR
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Reset
Value
0
DMA Channel Priority
Define the DMA channel priority relative to the other DMA channels and to the core priority
if an external bus access is required. For pending DMA transfers, the DMA controller
compares channel priority levels to determine which channel can activate the next word
transfer. This decision is required because all channels use common resources, such as
the DMA address generation logic, buses, and so forth.
• If all or some channels have the same priority, then channels are activated in a
• If channels have different priorities, the highest priority channel executes DMA transfers
• If a lower-priority channel is executing DMA transfers when a higher priority channel
• If some channels with the same priority are active in a round-robin fashion and a new
• The DPR bits also determine the DMA priority relative to the core priority for external bus
round-robin fashion—that is, channel 0 is activated to transfer one word, followed by
channel 1, then channel 2, and so on.
and continues for its pending DMA transfers.
receives a transfer request, the lower-priority channel finishes the current word transfer
and arbitration starts again.
higher-priority channel receives a transfer request, the higher-priority channel is granted
transfer access after the current word transfer is complete. After the higher-priority
channel transfers are complete, the round-robin transfers continue. The order of transfers
in the round-robin mode may change, but the algorithm remains the same.
access. Arbitration uses the current active DMA priority, the core priority defined by the
SR bits CP[1–0], and the core-DMA priority defined by the OMR bits CDP[1–0]. Priority of
core accesses to external memory is as follows:
DPR
00
01
10
11
DSP56303 User’s Manual, Rev. 2
Description
Priority level 3 (highest)
Priority level 0 (lowest)
Channel Priority
Priority level 1
Priority level 2
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