SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 16

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DSP56303 Overview
1.6 DSP56300 Core Functional Blocks
The functional blocks of the DSP56300 core are:
In addition, the DSP56303 provides a set of internal peripherals, discussed in
Section 1.9, Peripherals, on page 1-12.
1.6.1 Data ALU
The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
1.6.1.1 Data ALU Registers
The data ALU registers are read or written over the X data bus and the Y data bus as 16- or 32-bit
operands. The source operands for the data ALU can be 16, 32, or 40 bits and always originate
from data ALU registers. The results of all data ALU operations are stored in an accumulator.
Data ALU operations are performed in two clock cycles in a pipeline so that a new instruction
can be initiated in every clock cycle, yielding an effective execution rate of one instruction per
clock cycle. The destination of every arithmetic operation can be a source operand for the
immediately following operation without penalty.
1.6.1.2 Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit accepts as
1-6
Data arithmetic logic unit (ALU)
Address generation unit
Program control unit
PLL and clock oscillator
JTAG TAP and OnCE module
Memory
Fully pipelined 24 × 24-bit parallel multiplier-accumulator
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit
stream generation and parsing)
Conditional ALU instructions
Software-controllable 24-bit, 48-bit, or 56-bit arithmetic support
Four 24-bit or 48-bit input general-purpose registers: X1, X0, Y1, and Y0
Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general-purpose, 56-bit accumulators, A and B, accumulator shifters
Two data bus shifter/limiter circuits
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor