SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 89

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Number
18–17
cont.
Bit
16
Bit Name
DCON
DPR
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Reset
Value
0
• If DMA priority > core priority (for example, if CDP = 01, or CDP = 00 and
• If DMA priority = core priority (for example, if CDP = 10, or CDP = 00 and
• If DMA priority < core priority (for example, if CDP=11, or CDP = 00 and
• In Dynamic Priority mode (CDP = 00), the DMA channel can be halted before executing
DMA Continuous Mode Enable
Enables/disables DMA Continuous mode. When DCON is set, the channel enters the
Continuous Transfer mode and cannot be interrupted during a transfer by any other DMA
channel of equal priority. DMA transfers in the continuous mode of operation can be
interrupted if a DMA channel of higher priority is enabled after the continuous mode transfer
starts. If the priority of the DMA transfer in continuous mode (that is, DCON = 1) is higher
than the core priority (CDP = 01, or CDP = 00 and DPR > CP), and if the DMA requires an
external access, the DMA gets the external bus and the core is not able to use the external
bus in the next cycle after the DMA access even if the DMA does not need the bus in this
cycle. However, if a refresh cycle from the DRAM controller is requested, the refresh cycle
interrupts the DMA transfer. When DCON is cleared, the priority algorithm operates as for
the DPR bits.
OMR - CDP[1–0]
DPR > CP), the DMA performs the external bus access first and the core waits for the
DMA channel to complete the current transfer.
DPR = CP), the core performs all its external accesses first and then the DMA channel
performs its access.
DPR < CP), the core performs its external accesses and the DMA waits for a free slot in
which the core does not require the external bus.
both the source and destination accesses if the core has higher priority. If another
higher-priority DMA channel requests access, the halted channel finishes its previous
access with a new higher priority before the new requesting DMA channel is serviced.
00
00
00
00
01
10
11
DSP56303 User’s Manual, Rev. 2
CP[1–0]
00
01
10
11
xx
xx
xx
Description
DMA accesses have higher priority than
core accesses
DMA accesses have the same priority as
core accesses
DMA accesses have lower priority than core
accesses
DMA Control Registers 5–0 (DCR[5–0])
Core Priority
3 (highest)
0 (lowest)
1
2
4-31