SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 119

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6.7 Host Transmit (HTX) Register
The HTX register is used in DSP-to-host data transfers. The DSP56303 views it as a 24-bit
write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears the host transfer
data empty bit (HSR[HTDE]) on the DSP side. The contents of the HTX register are transferred
as 24-bit data to the Receive Data Registers (RXH:RXM:RXL) when both HSR[HTDE] and
receive data full (ISR[RXDF]) on the host-side bits are cleared. This transfer operation sets the
ISR[RXDF] and HSR[HTDE] bits. The DSP56303 can set the HCR[HTIE] bit to cause a host
transmit data interrupt when HSR[HTDE] is set. To prevent the previous data from being
overwritten, the DSP56303 should never write to the HTX when HSR[HTDE] is cleared.
Note:
6.6.8 Host Receive (HRX) Register
The HRX register is used in host-to-DSP data transfers. The DSP56303 views it as a 24-bit
read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the transmit data
Freescale Semiconductor
In a single-strobe mode, a DS (data strobe) signal qualifies the access, while a R/W (Read-Write)
signal specifies the direction of the access.
HRW
HDS
HWR
HRD
Data
Data
In dual-strobe mode, separate HRD and HWR signals specify the access as a read or write
access, respectively.
When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of the status bits
within the next two cycles, the bit does not reflect its current status. For details, see
Section 5.4.1, Polling, on page 1-3.
Read Cycle
Write Cycle
Figure 6-13. Single-Strobe Mode
Figure 6-14. Dual-Strobe Mode
DSP56303 User’s Manual, Rev. 2
Write Data In
Read Data Out
DSP Core Programming Model
6-19