SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 115

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6.4 Host Data Register (HDR)
The HDR register holds the data value of the corresponding bits of the HI08 signals configured as
GPIO signals. The functionality of Dxx depends on the corresponding HDDR bit (that is,
DRxx).The host processor can not access the Host Data Register (HDR)
6.6.5 Host Base Address Register (HBAR)
In multiplexed bus modes, HBAR selects the base address where the host-side registers are
mapped into the host bus address space. The address from the host bus is compared with the base
address as programmed in the Base Address Register. An internal chip select is generated if a
match is found. Figure 6-11 shows how the chip-select logic uses HBAR.
Freescale Semiconductor
1. Defined by the selected configuration.
Bit Number
HDDR
DRxx
D15
15
0
1
15–8
7–0
15
D14
14
—Reserved bit, read as 0, write to 0 for future compatibility.
Read-only bit—The value read is the binary value of
the signal. The corresponding signal is configured as
an input.
Read/write bit— The value written is the value read.
The corresponding signal is configured as an output
and is driven with the data written to Dxx.
14
Figure 6-10. Host Base Address Register (HBAR) (X:$FFFFC5)
D13
Table 6-11. Host Base Address Register (HBAR) Bit Definitions
13
Bit Name
BA[10–3]
13
D12
Figure 6-9. Host Data Register (HDR) (X:$FFFFC8)
12
12
GPIO Signal
Table 6-10. HDR and HDDR Functionality
D11
Reset Value
11
11
$80
0
D10
10
10
DSP56303 User’s Manual, Rev. 2
1
Reserved. Write to 0 for future compatibility.
Base Address
Reflect the base address where the host-side registers are mapped into
the bus address space.
D9
9
9
D8
8
8
BA10 BA9
D7
7
7
HDR
Dxx
Read-only bit—Does not contain significant data.
Read/write bit— The value written is the value read.
D6
6
6
BA8
5
D5
Description
5
BA7
Non-GPIO Signal
4
D4
4
BA6
DSP Core Programming Model
3
D3
3
BA5
2
D2
2
1
BA4
1
D1
1
BA3
0
D0
0
6-15