SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 283

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

G
general-purpose flags for host-DSP communication 6-6
General-Purpose Input/Output (GPIO) 1-12
Global Data Bus (GDB) 1-10
Ground 2-3
H
HACK signal 6-18
handshaking mechanisms
hardware stack 1-8
HI08 1-12
HI08 Interrupt Priority Level (HPL) bits 4-16
Host Acknowledge Enable (HAEN) bit 6-18
Host Acknowledge Polarity (HAP) bit 6-16
Host Address Line 8 Enable (HA8EN) 6-18
Host Address Line 9 Enable (HA9EN) 6-18
Host Address Strobe Polarity (HASP) bit 6-17
Host Base Address Register (HBAR) 6-12
Host Chip Select Enable (HCSEN) bit 6-18
Host Chip Select Polarity (HSCP) bit 6-17
Host Command (HC) bit 6-24
Host Command Interrupt Enable (HCIE) bit 6-13
Host Command Pending (HCP) bit 6-14
Host Control Register (HCR) 6-12
Host Data Direction Register (HDDR) 6-3
Host Data Direction Register (HDRR) 6-30
Host Data Register (HDR) 6-12
Host Data Strobe Polarity (HDSP) bit 6-17
Host Dual Data Strobe (HDDS) bit 6-17
Host Enable (HEN) bit 6-17
Host Flag 0 (HF0) bit 6-23
Host Flag 1 (HF1) bit 6-23
Host Flag 2 (HF2) bit 6-25
Host Flag 3 (HF3) bit 6-25
Freescale Semiconductor
functions 6-3
Host Data Direction Register (HDDR) 6-12
Host Data Register (HDR) 6-12
Port B 5-6
Port C 5-7
Port D 5-7
Port E 5-7
PLL 2-3
HI08 6-5
ISR
programming sheet B-19
Host Command Interrupt Enable (HCIE) 6-13
Host Flags 2,3 (HF) 6-12
Host Receive Interrupt Enable (HRIE) 6-13
Host Transmit Interrupt Enable (HTIE) 6-13
programming sheet B-20
programming sheet B-31
programming sheet B-31
Transmit Data Register Empty 6-25
,
6-15
,
6-28
,
6-30
,
6-30
,
,
,
,
6-15
6-12
2-2
7-19
DSP56303 User’s Manual, Rev. 2
,
,
,
,
6-30
2-17
6-30
6-14
Host Flags 0, 1 (HF) bits 6-14
Host Flags 2,3 (HF) bits 6-12
Host GPIO Port Enable (HGEN) bit 6-18
Host Interface (HI08) 2-2
chip-select logic 6-16
Command Vector Register (CVR) 6-7
configuring host request mode 6-8
control operating mode 6-16
core communication with HI08 registers 6-11
core interrupts
data registers 6-21
data strobe 6-3
Direct Memory Access (DMA) 6-8
DMA transfers and host bus 6-8
double-buffered mechanism 6-5
DSP core 6-5
DSP core interrupts 6-6
DSP interrupt routines 6-21
DSP-side
DSP-to-host
dual host request enabled 6-9
dual-strobe mode 6-19
enabling host requests 6-8
external host address inputs 6-27
external host programmer’s model 6-20
four kinds of reset 6-27
four reset types 6-20
general-purpose flags for host-DSP communication 6-6
GPIO configuration options 6-14
GPIO functions 6-3
HACK signal 6-18
HACK/HRRQ handshake flags 6-21
handshaking mechanisms 6-5
handshaking protocols 6-5
Host Command (HC) 6-24
Host Vector (HV) 6-24
programming sheet B-21
host command 6-7
receive data register full 6-7
transmit data empty 6-7
programming model 6-11
control registers 6-12
data registers 6-12
registers after reset 6-20
data word 6-2
handshaking protocols 6-2
interrupts 6-2
mapping 6-2
transfer modes 6-2
transfers 6-5
choosing 6-6
Core DMA access 6-5
host request 6-5
interrupts 6-5
pros and cons of polling 6-6
,
6-19
,
2-9
,
2-10
,
2-12
,
,
6-1
6-21
Index-5
Index