EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 10

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–4
Figure 2–3. Clock Multiplier Unit
Figure 2–4. Transmitter PLL
Notes to
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your
(2) The global clock line must be driven from an input pin only.
Arria GX Device Handbook, Volume 1
Inter-Transceiver Lines
selections, the MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors).
Global Clock
Dedicated
REFCLK0
Dedicated
REFCLK1
Inter-Transceiver Lines[2:0]
Figure
To
2–4:
(2)
CMU Block
Reference Clock
Global Clock (1),
Inter-Transceiver
Figure 2–3
The transmitter PLL multiplies the input reference clock to generate the high-speed
serial clock required to support the intended protocol. It implements a half-rate
voltage controlled oscillator (VCO) that generates a clock at half the frequency of the
serial data rate for which it is configured.
Figure 2–4
/2
/2
The reference clock input to the transmitter PLL can be derived from:
■
■
from REFCLKs,
Lines
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1)
of the associated transceiver block
PLD global clock network (must be driven directly from an input clock pin and
cannot be driven by user logic or enhanced PLL)
shows the block diagram of the clock multiplier unit.
shows the block diagram of the transmitter PLL.
Transmitter Channels [3:2]
Transmitter Channels [1:0]
INCLK
Transmitter
PLL
Frequency
Detector
Phase
down
up
/M
(1)
Pump + Loop
Central Clock
Gen Block
Divider Block
Divider Block
Gen Block
Local Clock
Local Clock
Charge
TX Clock
TX Clock
Filter
Divider
Block
Controlled
Oscillator
Voltage
Transmitter PLL
and Low-Speed Parallel Clocks
and Low-Speed Parallel Clocks
Transmitter High-Speed Serial
Transmitter High-Speed Serial
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
/L
(1)
Serial Clock
High Speed
Transceivers