EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 147

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 4: DC and Switching Characteristics
Power Consumption
Table 4–41. Series On-Chip Termination Specification for Left I/O Banks
Pin Capacitance
Table 4–42. Arria GX Device Capacitance
Power Consumption
© December 2009 Altera Corporation
25- R
50- R
3.3/2.5/1.8
50- R
R
C
C
C
C
C
C
Note to
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5 pF.
IOTB
IOL
CLKTB
CLKL
CLKL+
OUTFB
D
Symbol
Symbol
Table
S
S
S
3.3/2.5
1.5
4–42:
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed differential
receiver and transmitter pins.
Input capacitance on top/bottom clock input pins:
Input capacitance on left clock inputs:
Input capacitance on left clock inputs:
Input capacitance on dual-purpose clock output/feedback pins in PLL banks 11 and 12.
Internal series termination without
calibration (25- setting
Internal series termination without
calibration (50- setting
Internal series termination without
calibration (50- setting
Internal differential termination for
LVDS (100- setting)
Table 4–42
Altera offers two ways to calculate power for a design: the Excel-based PowerPlay
early power estimator power calculator and the Quartus II PowerPlay power analyzer
feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically used prior
to designing the FPGA in order to get an estimate of device power. The Quartus II
PowerPlay Power Analyzer provides better quality estimates based on the specifics of
the design after place-and-route is complete. The power analyzer can apply a
combination of user-entered, simulation-derived and estimated signal activities
which, combined with detailed circuit models, can yield very accurate power
estimates.
In both cases, these calculations should only be used as an estimation of power, not as
a specification.
Description
shows the Arria GX device family pin capacitance.
(Note 1)
Parameter
CLK0
CLK1
and
and
V
CCIO
V
CCIO
CLK2
CLK3
V
V
Conditions
CLK[4..7]
= 3.3/2.5/1.8V
CCIO
CCIO
= 3.3/2.5V
.
.
= 1.5V
= 2.5V
and
CLK[12..15]
Commercial
Max
±30
±30
±36
±20
Resistance Tolerance
Arria GX Device Handbook, Volume 1
.
Industrial
Max
±30
±30
±36
±25
Typical
5.0
6.1
6.0
6.1
3.3
6.7
Units
Units
%
%
%
%
pF
pF
pF
pF
pF
pF
4–25