EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 26

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–20
Loopback Modes
Figure 2–18. Transceiver Data Path in Serial Loopback
Arria GX Device Handbook, Volume 1
PLD
Logic
Array
f
f
Byte Deserializer
Byte deserializer takes in one-byte wide data from the 8B/10B decoder and
deserializes it into a two-byte wide data at half the speed. This allows clocking the
PLD-receiver interface at half the speed as compared to the receiver PCS logic. The
byte deserializer is bypassed in GIGE mode.
The byte ordering at the receiver output might be different than what was
transmitted. This is a non-deterministic swap, because it depends on PLL lock times
and link delay. If required, you must implement byte ordering logic in the PLD to
correct this situation.
For more information about byte serializer, refer to the
Architecture
Receiver Phase Compensation FIFO Buffer
A receiver phase compensation FIFO buffer is located at each receiver channel’s logic
array interface. It compensates for the phase difference between the receiver PCS
clock and the local PLD receiver clock. The receiver phase compensation FIFO is used
in all supported functional modes. The receiver phase compensation FIFO buffer is
eight words deep in PCI Express (PIPE) mode and four words deep in all other
modes.
For more information about architecture and clocking, refer to the
Architecture
Arria GX transceivers support the following loopback configurations for diagnostic
purposes:
■
■
■
■
Serial Loopback
Figure 2–18
RX Phase
Compen-
sation
Serial loopback
Reverse serial loopback
Reverse serial loopback (pre-CDR)
PCI Express (PIPE) reverse parallel loopback (available only in [PIPE] mode)
FIFO
TX Phase
Compen-
sation
FIFO
chapter.
chapter.
shows the transceiver data path in serial loopback.
Serializer
Byte
De-
Serializer
Byte
Decoder
8B/10B
Encoder
8B/10B
Match
FIFO
Rate
Transmitter PCS
Receiver PCS
Aligner
Word
Arria GX Transceiver
Receiver PMA
Serializer
© December 2009 Altera Corporation
De-
Transmitter PMA
Serial Loopback
Chapter 2: Arria GX Architecture
Serializer
Recovery
Clock
Unit
Arria GX Transceiver
Transceivers