EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 221

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path
Table 4–111. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path
Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path
© December 2009 Altera Corporation
LVDS
Note to
(1)
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
LVPECL
Note to
(1)
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
Maximum DCD (ps) for Row DDIO Output I/O Standard
DDIO Column Output I/O
Maximum DCD (ps) for
Maximum DCD (ps) for
Row DDIO Output I/O
Table 4–110
Table 4–111
Table
Table
Standard
Standard
4–110:
4–111:
assumes the input clock has zero DCD.
assumes the input clock has zero DCD.
3.3/2.5V
180
3.3/2.5V
440
390
375
325
430
355
350
335
320
330
330
330
330
180
TTL/CMOS
TTL/CMOS
Input I/O Standard (No PLL in the Clock Path)
Input IO Standard (No PLL in the Clock Path)
1.8/1.5V
180
1.8/1.5V
495
450
430
385
490
410
405
390
375
385
385
390
360
180
Arria GX Devices (PLL Output
SSTL-2
2.5V
180
–6 Speed Grade
Feeding DDIO)
105
100
100
75
90
75
70
SSTL-2
2.5V
170
120
105
160
180
SSTL/HSTL
90
85
80
65
70
60
60
60
90
1.8/1.5V
180
Arria GX Device Handbook, Volume 1
Note (1)
SSTL/HSTL
1.8/1.5V
LVDS
3.3V
180
160
110
100
155
100
180
95
75
70
65
80
70
70
70
Units
ps
ps
ps
ps
ps
ps
ps
(Note 1)
Units
ps
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
4–99