EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 64

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

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Digital Signal Processing Block
Arria GX Device Handbook, Volume 1
f
Table 2–12. M-RAM Row Interface Unit Signals (Part 2 of 2)
For more information about TriMatrix memory, refer to the
Memory Blocks in Arria GX Devices
The most commonly used DSP functions are finite impulse response (FIR) filters,
complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT)
functions, direct cosine transform (DCT) functions, and correlators. All of these use
the multiplier as the fundamental building block. Additionally, some applications
need specialized operations such as multiply-add and multiply-accumulate
operations. Arria GX devices provide DSP blocks to meet the arithmetic requirements
of these functions.
Each Arria GX device has two to four columns of DSP blocks to efficiently implement
DSP functions faster than ALM-based implementations. Each DSP block can be
configured to support up to:
■
■
■
Eight 9 × 9-bit multipliers
Four 18 × 18-bit multipliers
One 36 × 36-bit multiplier
Unit Interface Block
R0
R1
R2
R3
R4
R5
L4
L5
datain_a[56..42]
byteena_a[5..4]
datain_a[71..57]
byteena_a[7..6]
datain_b[14..0]
byteena_b[1..0]
datain_b[29..15]
byteena_b[3..2]
datain_b[35..30]
addressb[4..0]
addr_ena_b
clock_b
clocken_b
renwe_b
aclr_b
addressb[15..5]
datain_b[41..36]
datain_b[56..42]
byteena_b[5..4]
datain_b[71..57]
byteena_b[7..6]
chapter.
Input Signals
dataout_a[59..48]
dataout_a[71..60]
dataout_b[11..0]
dataout_b[23..12]
dataout_b[35..24]
dataout_b[47..36]
dataout_b[59..48]
dataout_b[71..60]
© December 2009 Altera Corporation
TriMatrix Embedded
Chapter 2: Arria GX Architecture
Output Signals
Digital Signal Processing Block