EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 152

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–30
Table 4–45. Timing Measurement Methodology for Input Pins
Arria GX Device Handbook, Volume 1
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
(6)
(5)
(5)
(5)
(6)
(5)
(5)
I/O Standard
Figure 4–9. Measurement Setup for t
Table 4–45
Din
Din
OE
OE
specifies the input timing measurement setup.
V
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
2.325
1.660
CCIO
(V)
Measurement Conditions
zx
t
t
1 MΩ
1 MΩ
ZX
V
ZX
1.163
1.163
0.830
0.830
0.830
0.830
0.688
0.688
0.570
1.163
1.163
0.830
REF
, Tristate to Driving High
Dout
Dout
, Tristate to Driving Low
(Note
—
—
—
—
—
—
—
(V)
Dout
Dout
1), (2), (3),
Din
Din
OE
OE
Disable
Disable
Edge Rate (ns)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
2.325
1.660
(4)
Chapter 4: DC and Switching Characteristics
Enable
Enable
(Part 1 of 2)
½ V
½ V
© December 2009 Altera Corporation
CCINT
CCINT
t
t
zh
zl
Measurement Point
VMEAS (V)
1.5675
1.5675
1.1875
0.7125
1.1625
1.1625
0.6875
0.6875
1.1625
1.1625
0.855
1.485
1.485
0.570
0.83
0.83
0.83
0.83
0.83
½ V
½ V
“1”
“0”
CCIO
CCIO
I/O Timing Model