EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 225

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 4: DC and Switching Characteristics
PLL Timing Specifications
PLL Timing Specifications
Table 4–116. Enhanced PLL Specifications (Part 1 of 2)
© December 2009 Altera Corporation
f
f
f
f
t
t
t
f
f
t
f
f
t
t
f
f
f
f
% spread
t
t
t
IN
INPFD
INDUTY
ENDUTY
INJITTER
OUTJITTER
FCOMP
OUT
SCANCLK
CONFIGEPLL
OUT_EXT
OUTDUTY
LOCK
DLOCK
SWITCHOVER
CLBW
VCO
SS
PLL_PSERR
ARESET
ARESET_RECONFIG
Name
Input clock frequency
Input frequency to the PFD
Input clock duty cycle
External feedback input clock duty cycle
Input or external feedback clock input jitter
tolerance in terms of period jitter.
Bandwidth
Input or external feedback clock input jitter
tolerance in terms of period jitter.
Bandwidth  0.85 MHz
Dedicated clock output period jitter
External feedback compensation time
Output frequency for internal global or regional
clock
Scanclk frequency
Time required to reconfigure scan chains for
EPLLs
PLL external clock output frequency
Duty cycle for external clock output
Time required for the PLL to lock from the time
it is enabled or the end of device configuration
Time required for the PLL to lock dynamically
after automatic clock switchover between two
identical clock frequencies
Frequency range where the clock switchover
performs properly
PLL closed-loop bandwidth
PLL VCO operating range
Spread-spectrum modulation frequency
Percent down spread for a given clock
frequency
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Minimum pulse width on the areset signal
when using PLL reconfiguration. Reset the PLL
after scandone goes high.
Table 4–116
in both the commercial junction temperature range (0 to 85 C) and the industrial
junction temperature range (–40 to 100 C), except for the clock switchover and
phase-shift stepping features. These two features are only supported from the 0 to
100 C junction temperature range.

0.85 MHz
and
Description
Table 4–117
describe the Arria GX PLL specifications when operating
1.5
1.5
0.13
Min
300
100
500
1.5
0.4
40
40
—
—
50
—
—
—
45
—
—
—
10
2
2
(2)
(2)
174/f
0.03
100
Typ
0.5
1.0
1.2
0.5
—
—
—
—
—
—
—
SCANCLK
50
—
—
—
—
—
—
1
Arria GX Device Handbook, Volume 1
Max
16.9
500
420
250
550
100
500
840
500
±30
0.6
(1)
60
60
—
—
10
—
55
—
—
1
1
ns (peak-to-peak)
ns (peak-to-peak)
ps (p-p)
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
ms
ms
ns
ns
ps
ns
ns
%
%
%
%
4–103