EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 126

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–4
Table 4–6. Arria GX Transceiver Block AC Specification (Part 1 of 3)
Arria GX Device Handbook, Volume 1
Reference clock
Input reference clock frequency
Absolute V
Absolute V
Rise/Fall time
Duty cycle
Peak to peak differential input voltage V
(diff p-p)
Spread spectrum clocking
On-chip termination resistors
V
V
RREFB
Transceiver Clocks
Calibration block clock frequency
Calibration block minimum power-down
pulse width
fixedclk clock frequency
reconfig clock frequency
Transceiver block minimum power-down
pulse width
Receiver
Data rate
Absolute V
Absolute V
Maximum peak-to-peak differential input
voltage V
Minimum peak-to-peak differential input
voltage V
On-chip termination resistors
V
Bandwidth at 3.125 Gbps
ICM
ICM
ICM
(AC coupled)
(DC coupled)
(15)
ID
ID
M A X
MIN
MAX
MIN
(diff p-p)
(diff p-p)
Symbol / Description
for a
for a receiver pin
for a receiver pin
for a
(2)
REFCLK
REFCLK
(1)
Pin
(3)
Pin
(4)
ID
DC Gain = 3 dB
Vicm = 0.85 V
Vicm = 0.85 V
(PIPE) mode
Vicm = 1.2 V
PCI Express
Conditions
0 to –0.5%
BW = High
BW = Low
BW = Med
SDI mode
setting
setting
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
850 ± 10% 850 ± 10% 850 ± 10%
–6 Speed Grade Commercial and
1200 ±
10%
–0.3
0.25
–0.4
Min
200
100
600
160
2.5
50
—
—
45
30
10
30
—
—
—
—
—
2000 +/-1%
115 ± 20%
1200 ± 5%
125 ±10%
Industrial
100±15%
1200 ±
10%
Chapter 4: DC and Switching Characteristics
Typ
0.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
40
50
© December 2009 Altera Corporation
622.08
1200 ±
2000
3125
0.55
10%
Max
125
3.3
2.0
3.3
—
—
55
33
—
50
—
—
—
—
—
—
Operating Conditions
Mbps
Units
MHz
MHz
MHz
MHz
MHz
kHz
mV
mV
mV
mV
mV
ns
ns
UI
%



V
V
V
V
V
V