EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 40

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–34
ALM Operating Modes
Arria GX Device Handbook, Volume 1
One ALM contains two programmable registers. Each register has data, clock, clock
enable, synchronous and asynchronous clear, asynchronous load data, and
synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive the register's
clock and clear control signals. Either general-purpose I/O pins or internal logic can
drive the clock enable, preset, asynchronous load, and asynchronous load data. The
asynchronous load data input comes from the datae or dataf input of the ALM,
which are the same inputs that can be used for register packing. For combinational
functions, the register is bypassed and the output of the LUT drives directly to the
outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register output can drive these output drivers
independently (refer to
can drive column, row, or direct link routing connections. One of these ALM outputs
can also drive local interconnect resources. This allows the LUT or adder to drive one
output while the register drives another output. This feature, called register packing,
improves device utilization because the device can use the register and combinational
logic for unrelated functions. Another special packing mode allows the register
output to feed back into the LUT of the same ALM so that the register is packed with
its own fan-out LUT. This feature provides another mechanism for improved fitting.
The ALM can also drive out registered and unregistered versions of the LUT or adder
output.
The Arria GX ALM can operate in one of the following modes:
■
■
■
■
Each mode uses ALM resources differently. Each mode has 11 available inputs to the
ALM (refer to
carry-in from the previous ALM or LAB; the shared arithmetic chain connection from
the previous ALM or LAB; and the register chain connectionare directed to different
destinations to implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load,
and clock enable control for the register. These LAB-wide signals are available in all
ALM modes. For more information about LAB-wide control signals, refer to
Control Signals” on page
The Quartus II software and supported third-party synthesis tools, in conjunction
with parameterized functions such as library of parameterized modules (LPM)
functions, automatically choose the appropriate mode for common functions such as
counters, adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which ALM operating mode to use for
optimal performance.
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Figure
2–28)the eight data inputs from the LAB local interconnect;
Figure
2–30.
2–29). For each set of output drivers, two ALM outputs
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
“LAB