EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 220

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–98
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path
Arria GX Device Handbook, Volume 1
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
To calculate the DCD as a percentage:
Therefore, the DCD percentage for the output clock at 267 MHz is from 46.66% to
53.33%.
Table 4–109. Maximum DCD for Non-DDIO Output on Column I/O Pins
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL-12
LVPECL
Column I/O Output Standard I/O Standard
(T/2 – DCD) / T = (3,745 ps/2 – 125 ps) / 3,745 ps = 46.66% (for low boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 125 ps) / 3,745 ps = 53.33% (for high boundary)
3.3/2.5V
440
390
375
325
430
355
350
335
330
330
TTL/CMOS
Input I/O Standard (No PLL in the Clock Path)
1.8/1.5V
495
450
430
385
490
410
405
390
385
390
SSTL-2
2.5V
170
120
105
160
90
85
80
65
60
60
for Non-DDIO Output
Maximum DCD (ps)
–6 Speed Grade
SSTL/HSTL
1.8/1.5V
160
110
100
155
95
75
70
65
70
70
220
175
155
110
215
135
130
115
100
110
110
115
200
80
80
Chapter 4: DC and Switching Characteristics
© December 2009 Altera Corporation
Note (1)
LVDS
3.3V
105
135
100
105
110
105
75
90
85
90
Units
Duty Cycle Distortion
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps