EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 74

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–68
Figure 2–55. Regional Clocks
Arria GX Device Handbook, Volume 1
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-RCLK by driving two
RCLK network lines in adjacent quadrants (one from each quadrant), which allows
logic that spans multiple quadrants to use the same low skew clock. The routing of
this clock signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single quadrant.
Internal logic-array routing can also drive a dual-regional clock. Clock pins and
enhanced PLL outputs on the top and bottom can drive horizontal dual-regional
clocks. Clock pins and fast PLL outputs on the left and right can drive vertical
dual-regional clocks, as shown in
dual-regional clocks.
CLK[3..0]
7
1
2
8
RCLK
RCLK
[3..0]
[7..4]
[31..28]
RCLK
RCLK
[11..8]
CLK[15..12]
CLK[7..4]
11 5
12 6
Figure
[27..24]
[15..12]
RCLK
RCLK
2–56. Corner PLLs cannot drive
[23..20]
[19..16]
RCLK
RCLK
Transceiver
Transceiver
Arria GX
Arria GX
Block
Block
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks