EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 88

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

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Figure 2–67. Arria GX IOE Structure
Arria GX Device Handbook, Volume 1
Logic Array
Output B
Output A
Input B
Input A
The IOE in Arria GX devices contains a bidirectional I/O buffer, six registers, and a
latch for a complete embedded bidirectional single data rate or DDR transfer.
Figure 2–67
(plus a latch), two output registers, and two output enable registers. The design can
use both input registers and the latch to capture DDR input and both output registers
to drive DDR outputs. Additionally, the design can use the output enable (OE)
register for fast clock-to-output enable timing. The negative edge-clocked OE register
is used for DDR SDRAM interfacing. The Quartus II software automatically
duplicates a single OE register that controls multiple output or bidirectional pins.
The IOEs are located in I/O blocks around the periphery of the Arria GX device.
There are up to four IOEs per row I/O block and four IOEs per column I/O block.
Row I/O blocks drive row, column, or direct link interconnects. Column I/O blocks
drive column interconnects.
OE
Output Register
Output Register
shows the Arria GX IOE structure. The IOE contains two input registers
D
D
Q
Q
CLK
OE Register
OE Register
D
D
Q
Q
Input Register
Input Register
D
D
Q
Q
© December 2009 Altera Corporation
Input Latch
D
ENA
Chapter 2: Arria GX Architecture
Q
I/O Structure