EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 27

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
Transceivers
Figure 2–19. Arria GX Block in Reverse Serial Loopback Mode
© December 2009 Altera Corporation
FPGA
Logic
Array
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
RX Phase
Compen-
Verify
BIST
BIST
sation
FIFO
Compensation
TX Phase
1
FIFO
In GIGE and Serial RapidIO modes, you can dynamically put each transceiver
channel individually in serial loopback by controlling the rx_seriallpbken port. A
high on the rx_seriallpbken port puts the transceiver into serial loopback and a
low takes the transceiver out of serial loopback.
As seen in
back to the receiver CRU in serial loopback. The transmitter data path from the PLD
interface to the serializer in serial loopback is the same as in non-loopback mode. The
receiver data path from the clock recovery unit to the PLD interface in serial loopback
is the same as in non-loopback mode. Because the entire transceiver data path is
available in serial loopback, this option is often used to diagnose the data path as a
probable cause of link errors.
When serial loopback is enabled, the transmitter output buffer is still active and
drives the serial data out on the tx_dataout port.
Reverse Serial Loopback
Reverse serial loopback mode uses the analog portion of the transceiver. An external
source (pattern generator or transceiver) generates the source data. The high-speed
serial source data arrives at the high-speed differential receiver input buffer, passes
through the CRU unit and the retimed serial data is looped back, and is transmitted
though the high-speed differential transmitter output buffer.
Figure 2–19
Serializer
Byte
Figure
shows the data path in reverse serial loopback mode.
20
serializer
Byte
De-
Encoder
8B/10B
2–18, the serial data output from the transmitter serializer is looped
Decoder
8B/10B
Generator
PRBS
BIST
Match
Rate
FIFO
Deskew
FIFO
PRBS
Verify
BIST
Aligner
Word
Arria GX Device Handbook, Volume 1
Analog Receiver and
Transmitter Logic
Serializer
serializer
De-
Reverse
Serial
Loopback
Recovery
Clock
Unit
2–21