MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 225

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
CPU32+
Also, note that the use of a 32-bit data bus reduces external bus utilization by 19 to 28 per-
centage points (e.g., 78–50 = 28%). This reduction gives more time for peripherals, such as
DMA channels, to use the bus without adversely affecting overall system performance. In
the best case, the CPU32+ can use as little as 50% of the bus, even though instructions exe-
cute continuously.
5.7.1 Resource Scheduling
The CPU32+ contains several independently scheduled resources. The organization of
these resources within the CPU32+ is shown in Figure 5-30. Some variation in instruction
execution timing results from concurrent resource utilization. Because resource scheduling
is not directly related to instruction boundaries, it is impossible to make an accurate predic-
tion of the time required to complete an instruction without knowing the entire context within
which the instruction is executing.
5.7.1.1 MICROSEQUENCER. The microsequencer either executes microinstructions or
awaits completion of accesses necessary to continue microcode execution. The microse-
quencer supervises the bus controller, instruction execution, and internal processor opera-
tions such as calculation of EA and setting of condition codes. It also initiates instruction
word prefetches after a change of flow and controls validation of instruction words in the
instruction pipeline.
5.7.1.2 INSTRUCTION PIPELINE. The CPU32+ contains a two-word instruction pipeline
where instruction opcodes are decoded. Each stage of the pipeline is initially filled under
microsequencer control and subsequently refilled by the prefetch controller as it empties.
Stage A of the instruction pipeline is a buffer. Prefetches completed on the bus before stage
B empties are temporarily stored in this buffer. Instruction words (instruction operation
words and all extension words) are decoded at stage B. Residual decoding and execution
occur in stage C.
Each pipeline stage has an associated status bit that shows whether the word in that stage
was loaded with data from a bus cycle that terminated abnormally.
5.7.1.3 BUS CONTROLLER RESOURCES. The bus controller consists of the instruction
prefetch controller, the write pending buffer, and the microbus controller. These three
resources transact all reads, writes, and instruction prefetches required for instruction exe-
cution.
The bus controller and microsequencer operate concurrently. The bus controller can per-
form a read or write or schedule a prefetch while the microsequencer controls EA calculation
or sets condition codes.
The microsequencer can also request a bus cycle that the bus controller cannot perform
immediately. When this happens, the bus cycle is queued, and the bus controller runs the
cycle when the current cycle has completed.
MOTOROLA
MC68360 USER’S MANUAL
5-83
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