MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 433

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

For synchronous communication, the internal clock is identical to the baud rate output. To
get the desired rate, the user can select the appropriate system clock according to the fol-
lowing equation:
sync baud rate = (BRGCLK or CLK2 or CLK6)
the DIV16 bit)
For example, to get the rate of 64 kbps, the system clock can be 24.96 MHz, DIV16 = 0, and
the clock divider = 389.
7.10 SERIAL COMMUNICATION CONTROLLERS (SCCS)
The SCC key features are as follows:
MOTOROLA
• Implements HDLC/SDLC, HDLC Bus, BISYNC, Synchronous Start/Stop, Asynchro-
• Ethernet Version of QUICC Supports Full 10 Mbps Ethernet/IEEE 802.3 on SCC1
• Additional Protocols Supported Through Motorola-Supplied RAM Microcodes: Profi-
• 2 Mbps HDLC, HDLC Bus, and/or Transparent Data Rates Supported on All Four SCCs
• 10 Mbps Ethernet (Half Duplex) on SCC1 and 2 Mbps on the Other SCCs Supported
• A Single HDLC or Transparent Channel Can Be Supported at 8 Mbps (Full Duplex)
• SCC Clocking Rates up to 12.5 MHz at 25 MHz.
• DPLL Circuitry for Clock Recovery with NRZ, NRZI, FM0, FM1, Manchester, and Differ-
• SCC Clocks May Be Derived from a Baud Rate Generator, an External Pin, or DPLL.
• Supports Automatic Control of the RTS, CTS, and CD Modem Signals
• Multibuffer Data Structure for Receive and Transmit (up to 224 BDs May Be Partitioned
• Deep FIFOs (SCC1 Has 32-Byte Rx and Tx FIFOs; SCC2, SCC3, and SCC4 Have 16-
• Transmit-On-Demand Feature Decreases Time to Frame Transmission
• Low FIFO Latency Option for Transmit and Receive in Character-Oriented and Totally
• Frame Preamble Options
• Full-Duplex Operation
• Fully Transparent Option for Receiver/Transmitter While Another Protocol Executes on
• Echo and Local Loopback Modes for Testing
nous Start/Stop (UART), AppleTalk (LocalTalk), and Totally Transparent Protocols
bus, Signaling System#7 (SS7), Async HDLC, DDCMP, V.14, and X.21 (see Appendix
C RISC Microcode from RAM).
Simultaneously (Full Duplex).
Simultaneously (Full Duplex)
ential Manchester (Also Known as Differential Biphase-L)
Data Clock May Be as High as 3.125 MHz with a 25-MHz Clock
in Any Way Desired)
Byte Rx and Tx FIFOs)
Transparent Protocols
the Transmitter/Receiver
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
(clock divider + 1)
Serial Communication Controllers (SCCs)
(1 or 16 according to
7-109