MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 703

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

HP4–HP0—Highest Priority
VBA2–VB0—Vector Base Address
Bits 4–1—Reserved
SPS—Spread Priority Scheme
7.15.5.2 CPM INTERUPT PENDING REGISTER (CIPR). Each bit in the 32-bit read-write
CIPR corresponds to a CPM interrupt source. When a CPM interrupt is received, the CPIC
sets the corresponding bit in the CIPR.
In a vectored interrupt scheme, the CIPR clears the CIPR bit when the vector number cor-
responding to the CPM interrupt source is passed during an interrupt acknowledge cycle,
unless an event register exists for that interrupt source. (Event registers exist for interrupt
sources that have multiple source events. For example, the SCCs have multiple events that
can cause an SCC interrupt.)
In a polled interrupt scheme, the user must periodically read the CIPR. When a pending
interrupt is handled, the user clears the corresponding bit in the CIPR. (However, if an event
register exists, the unmasked event register bits should be cleared instead, causing the
CIPR bit to be cleared.) To clear a bit in the CIPR, the user writes a one to that bit. Since the
user can only clear bits in this register, bits written as zeros will not be affected. The CIPR
is cleared at reset.
MOTOROLA
PC0
PC4
These bits specify the 5-bit interrupt number of the single CPIC interrupt source that is to
be advanced to the highest priority in the table. These bits may be dynamically modified.
To keep the original priority order intact, simply program these bits to 11111.
These three bits are concatenated with five bits provided by the CPIC for each specific
interrupt source to form an 8-bit interrupt vector number. If these bits are not written, the
uninitialized vector (value $0F) is provided for all CPM sources. These bits should not be
dynamically modified.
This bit, which selects the relative SCC priority scheme, may not be changed dynamically.
31
15
0 = Grouped. The SCCs are grouped in priority at the top of the table.
1 = Spread. The SCCs are spread in priority throughout the table.
SCC1
PC5
30
14
SCC2
29
13
The SCC CIPR bit positions are NOT changed according to the
relative priority between SCCs (as determined by the SCxP and
SPS bits in the CICR).
No bit in the CIPR is set if the error vector is issued.
—
TIMER3
SCC3
28
12
Freescale Semiconductor, Inc.
SCC4
PC6
27
11
For More Information On This Product,
PC1
PC7
26
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
TIMER1
PC8
25
9
PC2
NOTES
24
—
8
TIMER4
PC3
23
7
SDMA
PC9
22
6
IDMA1
SPI
21
5
CPM Interrupt Controller (CPIC)
IDMA2
SMC1
20
4
SMC2 /
PIP
19
—
3
TIMER2
PC10
18
2
PC11
R–TT
171
1
7-379
16
—
—
0