MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 446

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
Bits 14–0—Reserved
7.10.6 SCC Buffer Descriptors
Data associated with each SCC channel is stored in buffers. Each buffer is referenced by a
BD, which may be located anywhere in internal memory. The QUICC internal memory has
space for 224 BDs to be shared between the four SCCs and any SMCs and SPIs that are
used. However, the allocation of BDs to the transmitter or receiver of a serial channel is
user-defined. Thus, the user may select 100 BDs for the SCC1 receiver, 20 BDs for the
SCC1 transmitter, etc.
The BD table forms a circular queue with a programmable length. The user can program the
start address of each channel BD table in the internal memory (see Figure 7-38). The user
is allowed to allocate the parameter area of an unused channel to the other used channels
as BD tables or as actual buffers.
The format of the BDs is the same for each SCC mode of operation and for both transmit
and receive. The first word in each BD contains a status and control word, which also deter-
mines the BD table length. Only this first field (containing the status and control bits) differs
for each protocol. The second word determines the data length referenced to this BD, and
the two last words in the BD contain the 32-bit address pointer that points to the actual buffer
in memory.
For frame-oriented protocols, a message may reside in as many buffers as necessary
(transmit or receive). Each buffer has a maximum length of (64K–1)bytes. The CP does not
assume that all buffers of a single frame are currently linked to the BD table; it does assume,
however, that the unlinked buffers will be provided by the CPU32+ core in time to be either
transmitted or received. Failure to do so will result in an error condition being reported by
the CP. An underrun error is reported in the case of transmit, and a busy error is reported in
the case of receive.
7-122
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
These bits should be written with zeros.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
HIGH-ORDER DATA BUFFER POINTER
LOW-ORDER DATA BUFFER POINTER
STATUS AND CONTROL
DATA LENGTH
150
MOTOROLA