MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 438

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
CDS—CD Sampling
CTSS—CTS Sampling
TFL—Transmit FIFO Length
RFW—Rx FIFO Width
TXSY—Transmitter Synchronized to the Receiver
7-114
The TXSY bit is particularly intended for X.21 applications where the transmitted data
must begin an exact multiple of 8-bit periods after the receive data arrives.
0 = The CD input is assumed to be asynchronous with the data. It is internally synchro-
1 = The CD input is assumed to be synchronous with the data, giving faster operation.
0 = The CTS input is assumed to be asynchronous with the data. It is internally syn-
1 = The CTS input is assumed to be synchronous with the data, giving faster operation.
0 = Normal operation. The transmit FIFO is 32 bytes for SCC1 and 16 bytes for the oth-
1 = The transmit FIFO is 1 byte. This may be used with character-oriented protocols
0 = Rx FIFO is 32-bits wide for maximum performance. Data will not normally be writ-
1 = Low-latency operation. The Rx FIFO is 8-bits wide, and the receive FIFO is one-
0 = No synchronization between receiver and transmitter (default).
1 = The transmit bit stream is synchronized to the receiver. Additionally, if RSYN = 1,
nized by the SCC, and then data is received.
In this mode, CD must transition while the receive clock is in the low state. As soon
as CD is low, data begins being received. This mode is especially useful when con-
necting QUICCs in transparent mode since it allows the RTS pin of one QUICC to
be directly connected to the CD pin of the other QUICC.
chronized by the SCC, and data is then transmitted after several serial clock de-
lays.
In this mode, CTS must transition while the transmit clock is in the low state. As
soon as CTS is low, data immediately begins transmission. This mode is especially
useful when connecting QUICCs in transparent mode since it allows the RTS pin
of one QUICC to be directly connected to the CTS pin of the other QUICC.
er SCCs.
such as UART to ensure a minimum FIFO latency at the expense of performance.
ten to receive buffers until at least 32 bits have been received. This configuration
is required for HDLC-type protocols and Ethernet; it is the recommended configu-
ration for high-performance transparent modes. In this mode, the receive FIFO is
32 bytes for SCC1 and 16 bytes for the other SCCs.
fourth its normal size (8 bytes for SCC1 and 4 bytes for the other SCCs). This al-
lows data to be written to the data buffer each time a character is received, without
waiting for 32 bits to be received. This configuration must be chosen for character-
oriented protocols such as UART and BISYNC. It may also be used for low-perfor-
mance, low-latency, totally transparent operation if desired. It must not be used
with HDLC, HDLC Bus, AppleTalk, or Ethernet, or erratic behavior may result.
then transmission in the totally transparent mode will not occur until the receiver
has synchronized with the bit stream and the CTS signal is asserted to the SCC.
Assuming CTS is already asserted, transmission will begin eight clocks after the
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