MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 534

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
register refers to the PSMR of the SCC when that SCC is configured for BISYNC mode. This
register is cleared at reset. Some of the PSMR bits can be modified on the fly (i.e., while the
receiver and transmitter are enabled).
NOS—Minimum Number of SYNCs Between or Before Messages
CRC—CRC Selection
RBCS—Receive Block Check Sequence
RTR—Receiver Transparent Mode
7-210
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If NOS3–NOS0 = 0000, then 1 SYN1–SYN2 pair will be transmitted; if NOS3–NOS0 =
1111, then 16 SYN1–SYN2 pairs will be transmitted. The SYN1–SYN2 pair is defined in
the DSR. The entire SYN1–SYN2 pair will always be transmitted regardless of the setting
of the SYNL bits in the GSMR. The NOS bits may be modified on the fly.
The BISYNC receiver internally stores two BCS calculations with a byte delay (eight serial
clocks) between them. This enables the user to examine a received data byte and then
decide whether or not it should be part of the BCS calculation. This is useful when control
character recognition and stripping are to be performed in software. The bit should be set
(or reset) within the time taken to receive the following data byte. When this bit is reset,
the BCS calculations exclude the latest fully received data byte. When RBCS is set, the
BCS calculations continue normally.
00 = Reserved.
01 = CRC16 (BISYNC). (X16 + X15 + X2 + 1). The PRCRC and PTCRC registers
10 = Reserved
11 = LRC (sum check). (BISYNC). For even LRC, the PRCRC and PTCRC registers
0 = Disable receive BCS
1 = Enable receive BCS
0 = The receiver is placed in normal mode with SYNC stripping and control character
1 = The receiver is placed in transparent mode. SYNCs, DLEs, and control characters
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recognition operative.
are only recognized after a leading DLE character. The receiver will calculate the
CRC16 sequence, even if it is programmed to LRC while in transparent mode. PR-
CRC should be initialized to the CRC16 preset value before setting this bit.
NOS
should be initialized to a preset value of all zeros or all ones before the channel is
enabled. In both cases, the transmitter sends the calculated CRC non-inverted,
and the receiver checks the CRC against zero. Eight-bit data characters (without
parity) are configured when CRC16 is chosen.
should be initialized to zero before the channel is enabled. For odd LRC, the PR-
CRC and PTCRC registers should be initialized to ones.
The receiver will check character parity when BCS is programmed to LRC and the
receiver is not in transparent mode. The transmitter will transmit character parity
when BCS is programmed to LRC and the transmitter is not in transparent mode.
Use of parity in BISYNC assumes the use of 7-bit data characters.
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Freescale Semiconductor, Inc.
CRC
For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
RBCS
9
RTR
8
RVD
7
DRT
6
5
—
4
3
RPM
2
MOTOROLA
1
TPM
0