MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 552

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
7.10.21.7.2 Reception Errors. The following paragraphs describe various types of recep-
tion errors.
Overrun Error . The SCC maintains an internal FIFO for receiving data. The CP begins pro-
gramming the SDMA channel (if the data buffer is in external memory) and updating the
CRC when 8 or 32 bits (according to the RFW bit in the GSMR) are received in the FIFO. If
a FIFO overrun occurs, the SCC writes the received data byte to the internal FIFO over the
previously received byte. The previous character and its status bits are lost. Following this,
the channel closes the buffer, sets the OV bit in the BD, and generates the RX interrupt (if
enabled). The receiver then enters hunt mode immediately.
CD Lost During Message Reception . When this error occurs, the channel terminates mes-
sage reception, closes the buffer, sets the CD bit in the BD, and generates the RX interrupt
(if enabled). This error has the highest priority; the rest of the message is lost, and no other
errors are checked in the message. The receiver then enters hunt mode immediately.
7.10.21.8 TRANSPARENT MODE REGISTER (PSMR). The PSMR is called the transpar-
ent mode register when an SCC is programmed for transparent mode. However, since all
transparent mode selections are in the GSMR, this register is not used by the transparent
controller. If transparent mode is only selected for the transmitter/receiver, then the trans-
mitter/receiver may be programmed to support another protocol. In such a case, the PSMR
may be used for that other protocol.
7.10.21.9 TRANSPARENT RECEIVE BUFFER DESCRIPTOR (RX BD). •The CP reports
E—Empty
7-228
1. Detecting an error
2. Detecting a full receive buffer
3. Issuing the ENTER HUNT MODE command
4. Issuing the CLOSE Rx BD command
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
information about the received data for each buffer using an Rx BD. The CP closes the
current buffer, generates a maskable interrupt, and starts to receive data into the next
buffer after one of the following events:
0 = The data buffer associated with this Rx BD has been filled with received data, or
data reception has been aborted due to an error condition. The CPU32+ core is
free to examine or write to any fields of this Rx BD. The CP will not use this BD
again while the E-bit remains zero.
15
E
14
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Freescale Semiconductor, Inc.
For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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CM
RX DATA BUFFER POINTER*
9
DATA LENGTH
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8
DE
7
—
6
—
5
NO
4
—
3
CR
2
MOTOROLA
OV
1
CD
0