MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 542

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
A more efficient method is as follows. Multibyte buffers are prepared and linked to the
receive buffer table. Software is used to analyze the first two to three bytes of the buffer to
determine what type of block is being received. When this has been determined, reception
can continue without further intervention from the user’s software until a control character is
encountered. The control character signifies the end of the block, causing the software to
revert back to a byte-by-byte reception mode.
To accomplish this, the RCH bit in the BISYNC mask register should initially be set, enabling
an interrupt on every byte of data received to allow software to analyze the type of block
being received on a byte-by-byte basis. After analyzing the initial characters of a block, the
user should either set the RTR bit in the BISYNC mode register or issue the RESET BCS
CALCULATION command. For example, if DLE-STX is received, transparent mode should
be entered. By setting the appropriate bit in the BISYNC mode register, the BISYNC con-
troller automatically strips the leading DLE from <DLE-character> sequences. Thus, control
characters are only recognized when they follow a DLE character. The RTR bit should be
cleared after a DLE-ETX is received.
Alternatively, after receiving an SOH, the RESET BCS CALCULATION command should be
issued. This command causes the SOH to be excluded from BCS accumulation and the
BCS to be reset. Note that the RBCS bit in the BISYNC mode register (used to exclude a
character from the BCS calculation) is not needed here since SYNCs and leading DLEs (in
transparent mode) are automatically excluded by the BISYNC controller.
After recognizing the type of block above, the RCH interrupt should be masked. Data recep-
tion then continues without further interruption of the CPU32+ core until the end of the cur-
rent block is reached. This is defined by the reception of a control character matching that
programmed in the receive control characters table.
The control characters table should be set to recognize the end of the block as follows:
After the end of text (ETX), a BCS is expected; then the buffer should be closed. Hunt mode
should be entered when the line turnaround occurs (BISYNC is normally half-duplex). ENQ
characters are used to abort transmission of a block. For the receiver, the ENQ character
designates the end of the block, but no CRC is expected.
Following control character reception (i.e., end of the block), the RCH bit in the BISYNC
mask register should be set, reenabling interrupts for each byte of received data.
7.10.20.18 SCC BISYNC EXAMPLE. The following list is an initialization sequence for an
SCC BISYNC channel assuming an external clock is provided. SCC4 is used. The BISYNC
7-218
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Control Characters
MC68360 USER’S MANUAL
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ENQ
ETX
ETB
ITB
E
0
0
0
0
0
B
X
1
1
1
0
H
X
1
0
1
0
MOTOROLA