MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 439

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

SYNL—Sync Length (BISYNC and Transparent Mode Only)
RTSM—RTS Mode
RSYN—Receive Synchronization Timing (Valid for a Totally Transparent Channel Only)
EDGE—Clock Edge
MOTOROLA
These bits determine the operation of an SCC receiver that is configured for BISYNC or
totally transparent operation only. See the data synchronization register definition in the
BISYNC and totally transparent descriptions for more information.
This bit may be changed on the fly.
The EDGE bits determine the clock edge used by the DPLL for adjusting the receive sam-
ple point due to jitter in the received signal. The selection of the EDGE bits is ignored in
the UART protocol or the x1 mode of the RDCR bits.
00 = The sync pattern in the DSR is not used. An external sync signal is used instead
01 = 4-bit sync. The receiver will synchronize on a 4-bit sync pattern stored in DSR.
10 = 8-bit sync. This option should be chosen along with the BISYNC protocol to im-
11 = 16-bit sync. Also called BISYNC. The receiver will synchronize on a 16-bit sync
0 = Send idles between frames as defined by the protocol and the Tend bit. RTS is ne-
1 = Send flags/syncs between frames according to the protocol. RTS is always assert-
0 = Normal operation.
1 = If CDS = 1, then the CD pin should be asserted on the second bit of the receive
00 = Both the positive and negative edges are use for changing the sample point (de-
01 = Positive edge. Only the positive edge of the received signal is used for changing
10 = Negative edge. Only the negative edge of the received signal is used for changing
11 = No adjustment is made to the sample points.
receiver begins receiving data. This behavior is similar to the MC68302 totally
transparent mode behavior when the EXSYN bit in its SCC mode register is set.
gated between frames (default).
ed whenever the SCC is enabled.
frame, rather than the first. This configuration matches the behavior of the
MC68302 totally transparent receiver when its EXSYN bit is set; it is included on
the QUICC for compatibility.
(CD pin asserted).
This character and additional syncs can be programmed to be stripped using the
SYNC character in the parameter RAM. The transmitter will transmit the entire
contents of the DSR prior to each frame.
plement mono-sync. The receiver will synchronize on an 8-bit sync pattern stored
in DSR. The transmitter will transmit the entire contents of the DSR prior to each
frame.
pattern stored in DSR. The transmitter will transmit the DSR prior to each frame.
fault).
the sample point.
the sample point.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
7-115