MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 302

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
System Integration Module (SIM60)
When more wait states are programmed into the TCYC bits of the OR, the external AS (or
TS line) is synchronized internally.
The BADDR3–BADDR2 signals equal the A3–A2 signals when a burst is not in progress.
This configuration allows a non-bursting master to access the same memory as a bursting
external master by using the BADDR3–BADDR2 signals.
6.11.8 Global (Boot) Chip-Select Operation
Global (boot) chip-select operation allows address decoding for a boot ROM before system
initialization occurs. CS0 is the global chip-select output. Its operation differs from the other
external chip-select outputs following a system reset. When the CPU32+ begins accessing
memory after a system reset, CS0 is asserted for every address, unless the MBAR is
accessed or an internal peripheral on the IMB is accessed.
The global chip select provides a programmable port size at system reset using the CONFIG
pins. This capability allows a boot ROM to be located anywhere in the address space (with
up to 14 wait states), while still providing the stack pointer and program counter values at
$00000000 and $00000004, respectively. The global chip select does not provide write pro-
tection and responds to all function codes. CS0 operates in this manner until the first write
to the CS0 option register (OR0). CS0 can be programmed to continue decoding a range of
addresses after this write, provided the desired address range is first loaded into base reg-
ister 0. After the first write to the OR0, the global chip select can only be restarted with a
system reset.
6.11.9 SRAM Bus Error
The BERR signal may be asserted by the SRAM controller in the case of a parity error or by
the bus monitor of the SIM60 as a result of a write-protect violation. In addition, if the BERR
signal is asserted externally, it should not be asserted until at least S2 of the bus cycle.
6.12 DRAM CONTROLLER OVERVIEW (DRAM BANKS)
The DRAM controller supports a glueless interface to 16-bit (18 bit with parity) or 32-bit (36
bit with parity) DRAM or DRAM SIMMs from an internal QUICC master (CPU32+, IDMAs,
SDMAs). Many different DRAM bank sizes are supported: 128K, 256K, 512K, 1M, 2M, 4M,
8M, and 16M; thus, DRAMs such as 128K x 8, and 16M x 4 are supported. The DRAM con-
troller performs the address multiplexing for internal masters using the low-order address
lines.
Table 6-8 lists the physical address lines of the DRAM (row and column). In the case of a
16-bit DRAM port size with a 512K DRAM device (e.g., two 512K x 8 devices for a total of
16 bits wide), the row address to the DRAM bank will be A19–A10, and the column address
to the DRAM bank will be A9–A1. However, these signals will be internally multiplexed on
the A10–A1 pins; thus, the user should connect A10–A1 to the address pins on each 512K
DRAM device.
6-58
MC68360 USER’S MANUAL
MOTOROLA
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