TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 378

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

11.5
Description of Operations for Each Circuit
11.5.2
11.5.3
are built into each channel. If the comparator detects a match between a value set in this timer register and
that in a UC up-counter, it outputs the match detection signal.
fers. The double buffering is disabled in the initial state.
the double buffering becomes disable. If <TBWBF> = "1", it becomes enable. When the double buffering is en-
abled, a data transfer from the register buffer to the timer register (TBxRG0/1) is done in the case that UC is
matched with TBxRG1.When the counter is stopped even if double buffering is enabled, the double buffer-
ing operates as a single buffer, and an immediate data can be written to the TBxRG0 and TBxRG1.
UC is a 16-bit binary counter.
TBxRG0 and TBxRG1 are registers for setting values to compare with up-counter values and two registers
TBxRG0 and TBxRG1 are consisted of the double-buffered configuration which are paired with register buf-
Controlling double buffering disable or enable is specified by TBxCR<TBWBF> bit. If <TBWBF> = "0",
Up-counter (UC)
Timer registers (TBxRG0, TBxRG1)
・ Source clock
・ Counter start / stop
・ Timing to clear UC
・ UC overflow
- φT1, φT4 and φT16 - of prescaler output clock or the external clock of the TBxIN0 pin.
and stops counting and clears counter value if <TBRUN> = "0".
1. When a match is detected.
2. When UC stops
UC source clock, specified by TBxMOD<TBCLK[1:0]>, can be selected from either three types
Counter operation is specified by TBxRUN<TBRUN>. UC starts counting if <TBRUN> = "1",
If UC overflow occurs, the INTTBx overflow interrupt is generated.
match between counter value and the value set in TBxRG1. UC operates as a free-running coun-
ter if TBxMOD<TBCLE> = "0".
By setting TBxMOD<TBCLE> = "1", UC is cleared if when the comparator detects a
UC stops counting and clears counter value if TBxRUN<TBRUN> = "0".
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TMPM364F10FG