TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 463

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

13.4
13.4.1
13.4.2
13.4.3
nous serial interface functions.
and the receive buffers data in the 16-bit wide and 8-layered receive FIFO in receive mode. Serial data is transmit-
ted via SPDO and received via SPDI.
fsys . The operation mode, frame format, and data size of the SSP are programmed in the control registers
SSPCR0 and SSPCR1.
This LSI contains the SSP with 1channels.
The SSP is an interface that enables serial communications with the peripheral devices with three types of synchro-
The SSP performs serial-parallel conversion of the data received from a peripheral device.
The transmit buffers data in the independent 16-bit wide and 8-layered transmit FIFO in the transmit mode,
The SSP contains a programmable prescaler to generate the serial output clock SPCLK from the input clock
Overview of SSP
used to provide the serial output clock SPCLK.
in steps of two. Because the least significant bit of the SSPCPSR register is not used, division by an odd num-
ber is not possible.
ue programmed in the SSPCR0 register, to give the master output clock SPCLK.
When configured as a master, a clock prescaler comprising two free-running serially linked counters is
You can program the clock prescaler through the SSPCPSR register, to divide fsys by a factor of 2 to 254
The output of the prescaler is further divided by a factor of 1 to 256, which is obtained by adding 1 to the val-
Bitrate = fsys / (<CPSDVSR>×(1+<SCR>))
This is a 16-bit wide, 8-layered transmit FIFO buffer, which is shared in master and slave modes.
This is a 16-bit wide 8-layered receive FIFO buffer, which is shared in master and slave modes.
Clock prescaler
Transmit FIFO
Receive FIFO
f
sys
<CPSDVSR[7:1]>
Clock prescaler
(Depends on the setting)
Clock initial value
SSPCLKDIV
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1+<SCR[7:0]>
Toggle circuit
Divider circuit
Clock invert trigger
SPCLK
TMPM364F10FG