TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 818

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

27.6
AC Electrical Characteristics
27.6.3
27.6.3.1
OUTPUT DATA
INPUT DATA
(Outout mode/
SCLK Clock High width (input)
SCLK Clock Low width (input)
SCLK cycle
Output Data ←
SCLK rise / fall (Note1)
SCLK rise →
Output Data hold / fall (Note1)
Valid Data input ←
SCLK rise / fall (Note1)
SCLK rise →
Input Data hold / fall (Note1)
SCLK cycle (programmable)
Output Data ← SCLK rise
SCLK rise → Output Data hold
Valid Data input ← SCLK rise
SCLK rise → Input Data hold
fsys cycle time. It varies depending on the programming of the clock gear function.
Serial Interface (SIO/UART)
(1)
(2)
In the table below, the letter x represents the SIO operation clock cycle time which is identical to the
Input rise
(Input fall
I/O Interface mode
mode)
mode)
SCLK
SCLK
RxD
TxD
Note 1: SCLK rising edge / falling edge …Measured relative to the programmed active edge of SCLK.
Note 2: Keep this value positive by adjusting SCLK cycle.
SCLK Input mode
SCLK output mode
Parameter
Parameter
t
t
SRD
OSS
VALID
0
t
0
Symbol
Symbol
SCY
t
t
t
t
t
t
t
t
t
t
t
t
OHS
OHS
SCH
SCL
SCY
OSS
SRD
HSR
SCY
OSS
SRD
HSR
Page 792
t
SCY
t
t
t
SCH
SCY
SCY
/2 − 3x− 45
t
x + 30
SCY
Min
Min
/2 − 20
/2 − 20
4x
4x
30
4x
45
VALID
0
+ t
1
/2
Equation
Equation
1
SCL
t
SCH
t
HSR
t
OHS
Max
Max
−
−
−
−
−
−
−
−
−
−
−
−
t
SCL
VALID
2
2
−29.4
62.5
62.5
(íç2)
62.5
45.6
62.5
11.3
11.3
125
Min
Min
fsys = 64 MHz
fsys = 64 MHz
30
45
0
Max
Max
−
−
−
−
−
−
−
−
−
−
−
−
VALID
3
TMPM364F10FG
3
Unit
Unit
ns
ns