TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 590

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.5
Operation explain of each circuit
16.5.6
the time of message reception and transmission. The content of the CANTSC is written into the time stamp val-
ue (TSV) of the corresponding mailbox when a received message has been stored or a message has been trans-
mitted.
figuration mode or in sleep mode, the CANTSC will be stopped. After power-up reset, a write to the time
stamp counter prescaler register (CANTSP) clears the CANTSC to "0". The CANTSC is readable and writa-
ble from the CPU both in configuration mode and normal operation mode.
There is a free-running 16-bit time stamp counter (CANTSC) implemented in the CAN controller to show
The CANTSC is driven by the bit clock of the CAN bus line. When the operation mode of the CAN is in con-
Figure 16-5 shows the structure of the time stamp counter.
The free running time stamp counter and the time stamp hold register will be cleared in the following cases:
Time Stamp Function
Transmission/Reception
successful
・ After reset (Power on reset or software reset)
・ When the controller enters into configuration mode
・ When the controller enters into sleep mode
・ When a write access is performed to the CANTSP register.
CAN bus bit clock
MCU read/write
MCU read/write
Figure 16-5 Timer Stamp Counter
load
Time Stamp Hold Register
Time Stamp Counter
Prescaler Register
Prescaler (4 bit)
Free running
<TSC[15:0]>
MailBox RAM
<TSP[3:0]>
(16bit)
Page 564
Re-load value
Count-up clock
re-load
clear
clear
clear
Entering sleep mode
Entering configuration mode
Write to prescaler
Hardware/Software reset
Hardware/Software reset
Entering sleep mode
Entering configuration mode
Write to prescaler
TMPM364F10FG