TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 571

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.4.17
31-12
11
10
9
8
7
6
5
4
3
2
1
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
−
SUR
−
TSTLB
TSTERR
CCR
SMR
−
WUBA
MTOS
−
TSCC
Bit Symbol
CANMCR (Master Control Register)
CCR
31
23
15
0
0
0
7
1
-
-
-
R
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R/W
Type
SMR
30
22
14
0
0
0
6
0
Read : Read as "0".
Write : Write as "0".
Suspend mode request
0: Cancels suspend mode (normal operation)
1: Request suspend mode
Read : Read as "0".
Write : Write as "0".
Test loop back
0:Cancels test loop back mode (normal operation)
1:Request test loop back mode (This mode supports stand-alone operation.)
Test error
0:Cancels test error mode (normal operation)
1:Request test error mode (In this mode, it is possible to write the CAN error counter register (CANCEC)).
Change configuration request
0:Cancels configuration mode (normal operation)
1:Request configuration mode (In this mode, it possible to write the bit configuration registers, CANBCR1
and CANBCR2.)
Sleep mode request
0:Cancels sleep mode (normal operation)
1:Request sleep mode (In this mode, the clock of the CAN controller stops and the error counters and trans-
mit requests are reset.)
Read : Read as "0".
Write : Write as "0".
Walk-up on bus activity
0: Wakes up only by a write access to the CAMCR register.
1:Wakes up by detecting a bus active state or a write access to the CAMCR.
Mailbox transmission order select
0:Messages are transmitted in ascending order of mailbox number.
1:Messages in mailboxes are transmitted in descending order of message ID priority.
Read : Read as "0".
Write : Write as "0".
Time stamp counter clear
0: Disable
1:Clears the time stamp counter to "0". (note)
This bit is for write only and is read as always "0".
-
-
-
29
21
13
0
0
0
5
0
-
-
-
-
Page 545
WUBA
28
20
12
0
0
0
4
0
-
-
-
MTOS
SUR
27
19
11
Function
0
0
0
3
0
-
-
26
18
10
0
0
0
2
0
-
-
-
-
TSTLB
TSCC
25
17
0
0
9
0
1
0
-
-
TMPM364F10FG
TSTERR
SRES
24
16
0
0
8
0
0
0
-
-