TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 486

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

14.5
Control in the I2C Bus Mode
14.5
14.5.1
14.5.1.1
14.5.1.2
Control in the I2C Bus Mode
pin in the master mode.
that pulls its clock line to the "Low" level overrides other masters producing the "High" level on their
clock lines. This must be detected and responded by the masters producing the "High" level.
the "Low" level. Master B detects this transition, resets its "High" level period counter, and pulls its inter-
nal SCL output level to the "Low" level.
Serial Clock
SBIxCR1<SCK[2:0]> specifies the maximum frequency of the serial clock to be output from the SCL
The I2C bus is driven by using the wired-AND connection due to its pin structure. The first master
Clock synchronization assures correct data transfer on a bus that has two or more master.
For example, the clock synchronization procedure for a bus with two masters is shown below.
At the point a, Master A pulls its internal SCL output to the "Low" level, bringing the SCL bus line to
Note:The maximum speeds in the standard and high-speed modes are specified to 100kHz and
Internal SCL output
Internal SCL output
SCL line
Clock source
Clock Synchronization
400kHz respectively following the communications standards. Notice that the internal SCL
clock frequency is determined by the fsys used and the calculation formula shown above.
(Master A)
(Master B)
Figure 14-4 Example of Clock Synchronization
t
t
fscl = 1/(t
LOW
HIGH
=
= 2
= 2
2
n
fsys
n-1
n-1
LOW
+ 72
/fsys + 58/fsys
/fsys + 14/fsys
t
HIGH
+ t
Figure 14-3 Clock source
HIGH
a
Reset “High”level
period counting
)
t
LOW
Page 460
b
Wait for “High”level
period counting
SBIxCR1<SCK[2:0]>
c
1/fscl
000
001
010
011
100
101
110
Start “High” level period counting
10
11
n
5
6
7
8
9
TMPM364F10FG