TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 493

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

14.6
14.6.1
14.6.2
14.6.2.1
SBIxCR1
SBIxI2CAR
SBIxCR2
Data Transfer Procedure in the I2C Bus ModeI2C
at <ALS>. (<ALS> must be cleared to "0" when using the addressing format).
"High" first. Then write "0" to SBIxCR2<MST, TRX, BB>, "1" to <PIN>, "10" to <SBIM[1:0]> and "0" to
the bit 1 and 0.
First, program SBIxCR1<ACK, SCK[2:0]>. Writing "000" to SBIxCR1<BC[2:0]> at the time.
Next, program SBIxI2CAR by specifying a slave address at <SA[6:0]> and an address recognition mode
To configure the Serial Bus Interface as a slave receiver, ensure that the serial bus interface pin is at
edgment mode. Write to SBIxDBR a slave address and a direction bit to be transmitted.
on the bus. Following the start condition, the SBI generates nine clocks from the SCL pin. The SBI out-
puts the slave address and the direction bit specified at SBIxDBR with the first eight clocks, and releases
the SDA line in the ninth clock to receive an acknowledgment signal from the slave device.
"0". In the master mode, the SBI holds the SCL line at the "Low" level while <PIN> is = "0".<TRX>
changes its value according to the transmitted direction bit at generation of the INTSBIx interrupt re-
quest, provided that an acknowledgment signal has been returned from the slave device.
Device Initialization
Generating the Start Condition and a Slave Address
Note:Initialization of the serial bus interface circuit must be completed within a period that any device
Note:X; Don’t care
In the master mode, the following steps are required to generate the start condition and a slave address.
First, ensure that the bus is free (<BB> = "0"). Then, write "1" to SBIxCR1<ACK> to select the acknowl-
When <BB> = "0", writing "1111" to SBIxCR2<MST, TRX, BB, PIN> generates the start condition
The INTSBIx interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to
Note:To output salve address, check with software that the bus is free before writing to SBIxDBR. If this
Master mode
←
←
←
does not generate start condition after all devices connected to the bus were initialized. If this rule is
not followed, data may not be received correctly because other devices may start transfer before the
initialization of the serial bus interface circuit is completed.
rule is not followed, data being output on the bus may get ruined.
7
0
X
0
6
0
X
0
5
0
X
0
4
X
X
1
3
0
X
1
2
X
X
0
1
X
X
0
0
X
X
0
Page 467
Specifies ACK and SCL clock.
Specifies a slave address and an address recognition mode.
Configures the SBI as a slave receiver.
TMPM364F10FG