TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 545

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TMPM364F10FG

Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM364F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM364F10FG
Manufacturer:
Toshiba
Quantity:
10 000
Company:
Part Number:
TMPM364F10FG
Quantity:
6 000
15.4.3
15.4.3.1
Wait for bus
to be free
ing edge signal does not exit for specified bit cycles, and then sends a start bit. The confirmation of bus
free wait is performed all the time. Thus once bus free wait condition is satisfied, a transmission will
start soon when transmission setting is done.
buffer to the shift register. When the transmission of the first bit of the one byte data begins, transmission
interrupt is generates, and CECTSTAT<CECTISTA> is set. After transmission interrupt generation, next
one byte data is prepared to the transmit data buffer.
sion and ACK bit response confirmation.
ACK bit transmission and ACK bit response. By the end of transmission interrupt generates, CECT-
STAT<CECTIEND> is set.
Transmission
In the transmission setting, the CEC firstly confirms the bus free wait status; it checks whether a CEC fall-
After transmitting a start bit, CEC transmits one byte data and EOM data that are stored in the transmit
One byte data transmission completes in order of transmission of 8 bits data, EOM bit, ACK bit transmis-
Data transmission continues until EOM is set to "1".
If EOM is set to "1", the end of transmission interrupt generates after confirmation of data, EOM,
Interrupt generation ends a series of transmission process, and CECTEN<CECTEN> is cleared.
If an error is generated during transmission, an error interrupt is generates to stop transmission.
Even if reception is enabled, no reception is executed during transmission.
Basic Operation
S
H
D1
D2
(beginning of transmission)
Transmit interrupt
D3
Page 519
D4
Dn-2
(end of transmission)
Transmit interrupt
Dn-1
TMPM364F10FG
Dn

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