TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 583

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16.4.27
31-8
30-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
the mailbox is set to transmit, the corresponding bit in the CANMBRIF register is read as "0".
−
MBTIF30 to
MBTIF0
When the mailbox is set to receive, the corresponding bit in the CANMBTIF register is read as "0". When
Bit Symbol
CANMBTIF (Mailbox Transmit Interrupt Flag Register)
MBTIF23
MBTIF15
MBTIF7
31
23
15
0
0
0
7
0
-
R
R/W
Type
MBTIF30
MBTIF22
MBTIF14
MBTIF6
30
22
14
0
0
0
6
0
Read : Read as "0".
Write : Write as "0".
Mailbox transmit interrupt flag (Each bit corresponds with mailboxes 30 to 0.)
When the message in mailbox x has been successfully transmitted and the interrupt mask of the CAN-
MBIM register is enabled (<MBIMx>="1"), the <MBTIFx> bit is set to "1" and the transmit completion inter-
rupt (INTCANTX) becomes the "High" level.
When CANMBIM<MBIMx> bit is "0", the <MBTIFx> bit is not set and INTCANTX stays at the "Low" level.
Transmission completion is checked by reading the CANTA register.
If even one bit in the CANMBTIF register is "1", INTCANTX is the "High" level. The <MBTIFx> bit is
cleared by a write of "1" to the <MBTIFx> bit from the CPU.
A wirte of "0" is invalid.
MBTIF29
MBTIF21
MBTIF13
MBTIF5
29
21
13
0
0
0
5
0
Page 557
MBTIF28
MBTIF20
MBTIF12
MBTIF4
28
20
12
0
0
0
4
0
MBTIF27
MBTIF19
MBTIF11
MBTIF3
27
19
11
Function
0
0
0
3
0
MBTIF26
MBTIF18
MBTIF10
MBTIF2
26
18
10
0
0
0
2
0
MBTIF25
MBTIF17
MBTIF9
MBTIF1
25
17
0
0
9
0
1
0
TMPM364F10FG
MBTIF24
MBTIF16
MBTIF8
MBTIF0
24
16
0
0
8
0
0
0