TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 662

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.8
Restrictions on Using the USB Host Controller
18.8
Restrictions on Using the USB Host Controller
1. For an isochronous transfer, a Frame number to be transferred is defined in an Isochronous Transfer Descrip-
2. If a fatal error occurs on the USB system and the Host detects this error, the OHCI core sets HcInterrutSta-
3. After the software reset, OHCI registers are initialized. If a remote wakeup from the device occurs, the
4. When an overcurrent error occurs, if the HcRhDescriptorA.NPS[9] register has been set to "1", the
5. When the HcRhStatus.DRWE [15] is set to "1", a remote wakeup event does not cause a USBSUSPEND
6. In a system supporting overcurrent conditions, set the HcRhDescriptorA.NOCP [12] to "0".
tor (ITD). However, Frame numbers are not synchronized between the Host and software. If a descriptor
to be executed in a previous Frame is scheduled later, the Host determines that a time error has occurred
and writes back DATAOVERRUN to the CC field of the ITD. At this time, if the following conditions
are met, the Host will write back inappropriate status (NOERROR).
Frame number) - ITD.SF (transfer start Frame number).
linked.
tus.UE[4].
erated. After this interrupt is detected, a software reset (HcCommandStatus.HCR[0] = 0y1) is required to
recover from the Unrecoverable Error state and the Host then moves to the SUSPEND state.
Host remains in the SUSPEND state. When the remote wakeup function is used, a program for recover-
ing from the SUSPEND state must be prepared.
HcRhPortStatus1.PRS[4] and HcRhPortStatus1.PSS[2] bits are not cleared. Therefore, do not set the
HcRhDescriptorA.NPS[9] to "1" and the HcRhDescriptorB.DR[Port No] to "1".
to USBRESUME transition. When remote wakeup events are used, causing state transition by monitor-
ing to the HcInterruptStatus.RD[3] by the HCD. And when remote wakeup events are not used, do not
set the HcRhStatus.DRWE [15] to "1".
<Conditions>
The above problem occurs if transfers are scheduled in a way the following two conditions both true:
Where ITD.FC indicates the number of times an ITD is executed and R = HcFmNumber (current
Make sure that each ITD is synchronized to the current Frame number. If not, this ITD should not be
At this time, if the HcInterruptEnable.UE[4] register has been set additionally, a hardware interrupt is gen-
1 ITD.FC[2:0] = R[2:0]
2 ITD.FC[2:0] < R[15:0]
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TMPM364F10FG