TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 537
TMPM364F10FG
Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM364F10FG.pdf
(838 pages)
Specifications of TMPM364F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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15.4.2.2
<CECHNC[1:0]> = 10 (3 samplings)
<CECLNC[2:0]> = 011 (4 samplings)
CEC line
Sampling
clock
After
sampling
After
noise cancellation
trol Register 1 <CECRCR1>, the Receive Control Register 2 <CECRCR2> and the Receive Control Regis-
ter 3 <CECRCR3> are required.
(1)
(2)
Before receiving data, reception settings to the Logical Address Register <CECADD>, the Receive Con-
Preconfiguration
can be set simultaneously since every bit in this register corresponds with each address.
CECRCR1 register. It is considered as noise if "High"or "Low"of the same number as the specified val-
ue are not sampled.You can configure the time to detect "High" and "Low" respectively.
changed from "High" to "Low", the change is fully recognized if "Low"s of the same number as speci-
fied in the <CECLNC> bit are monitored. In the case that the CEC line is changed from "Low" to
"High", the change is fully recognized if "High" of the same number as specified in the
<CECHNC> bit are sampled.
<CECHNC [1:0]> = "10" (3 samplings) and <CECLNC[2:0]> = "011" (4 samplings). By cancelling
the noise, a signal "1" shifts to "0" after "0" is sampled four times. The signal "0" shifts to "1" after
"1" is sampled three times.
Configure logical address assigned to this product to the CECADD register. Multiple addresses
The noise cancellation time is configurable with the <CECHNC> and <CECLNC> bits of the
A CEC line is monitored at each rising edge of a sampling clock. In the case that the CEC line is
The following illustrates the operation of a case that a noise cancelling is configured as
Note:A broadcast message is received regardless of the CECADD register setting. By allocating a
Note:Use <CECLNC> in the same settings used for CECTCR<CECDTRS>.
Logical Address Configuration
Noise Cancellation Time
logical address of a device to 15, logical "0" is sent as an ACK response to the broadcast mes-
sage.
Page 511
TMPM364F10FG
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