TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 496

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

14.6
Data Transfer Procedure in the I2C Bus ModeI2C
SCLx pin
SDAx pin
<PIN>
INTSBIx
interrupt
request
SCLx pin
Write to SBIxDBR
SDAx pin
<PIN>
INTSBIx
interrupt request
(2)
Figure 14-10 <BC[2:0]>= "000",<ACK>= "1" (Transmitter Mode)
Figure 14-11 <BC[2:0]>= "000",<ACK>= "1" (Receiver Mode)
read from SBIxDBR to release the SCL line. (The data read immediately after transmission of a
slave address is undefined.)On reading the data, <PIN> is set to "1", and the serial clock is output
to the SCL pin to transfer the next data word.In the last bit, when the acknowledgment signal be-
comes the "Low" level, "0" is output to the SDA pin.
SCL pin to the "Low" level.Each time the received data is read from SBIxDBR, one-word transfer
clock and an acknowledgement signal are output.
ly before reading the data word second to last.
<BC[2:0]> must be set to "001" and the data must be read so that a clock is generated for 1-bit transfer.
end of transfer to the transmitter as an acknowledgment signal.
If the next data to be transmitted has eight bits, the transmit data is written into SBIxDBR.
If the data has different length, <BC[2:0]> and <ACK> are programmed and the received data is
After that, the INTSBIx interrupt request is generated, and <PIN> is cleared to "0", pulling the
To terminate the data transmission from the transmitter, <ACK> must be cleared to "0" immediate-
This disables generation of an acknowledgment clock for the last data word.
When the transfer is completed, an interrupt request is generated. After the interrupt processing,
At this time, the master receiver holds the SDA bus line at the "High" level, which signals the
Receiver mode (<TRX> = "0")
Read the received data
D7
1
D7
1
D6
2
D6
2
D5
3
D5
3
D4
4
D4
Page 470
4
D3
5
D3
5
D2
6
D2
6
D1
7
D1
7
D0
8
D0
8
ACK
9
Master output
Slave output
ACK
9
Acknowledgment signal
Master output
Slave output
Next D7
TMPM364F10FG
Acknowledgement
from receiver
to transmitter