TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 542

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

15.4
Operations
15.4.2.3
15.4.2.4
15.4.2.5
ception by enabling the CECREN <CECREN> bit. Detecting a start bit initiates the reception.
The received data is discarded.
form error), continue reception and send the reversed ACK response.
terrupts.
(1)
After configuring the CECADD, CECRCR1, CECRCR2 and CECRCR3 registers, CEC is ready for re-
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start bit.
It is possible to suspend a receive error interrupt (maximum cycle error, receive buffer overrun and wave-
You can check the interrupt factor by monitoring the bit of the CECRSTAT register corresponding to in-
Note:Changing the configurations of the CECADD, CECRCR1, CECRCR2 and CECRCR3 registers dur-
Enabling Reception
Detecting Error Interrupt
Details of reception error
riod does not comply with the specified minimum or maximum value, a cycle error interrupt is gener-
ated.
<CECMAX> bits. Maximum value is 90/fs (approx.2.747ms) and minimum value is 67/fs (approx.
2.045ms). It can be specified between the ranges −4/fs to +3/fs by the unit of 1/fs to detect cycle er-
rors.
erated.
ing reception may harm its proper operation. Before the change of the registers shown below, set
the CECREN <CECREN> bit to disable the reception and read the <CECREN> bit and the CECT-
EN <CECTRANS> bit to ensure that the operation is stopped.
Note 1: When minimum cycle error is detected, "Low" is output after "Low" detecting noise cancellation time.
Period between the falling edges of the two sequential bits is measured during reception. If the pe-
A setting of maximum cycle and minimum cycle time is specified by CECRCR1<CECMIN> and
The CECRSTAT <CECRIMIN> bit or the <CECRIMAX> bit is set if a cycle error interrupt is gen-
The minimum cycle error causes CEC to output "Low" for approx. 3.63 ms.
CECADD
CECRCR1
CECRCR2
CECRCR3
Register name
Cycle error
<CECADD[15:0]>
<CECHNC><CECLNC>
<CECMIN><CECMAX>
<CECOTH>
<CECSWAV0><CECSWAV1>
<CECSWAV2><CECSWAV3>
<CECWAV0><CECWAV1>
<CECWAV2><CECWAV3>
Bit Symbol
Page 516
Logical address
Noise cancellation time
Time to identify cycle error
Data reception at logical address discrep-
ancy
Start bit detection
Waveform error detection (when enabled)
Setting item
TMPM364F10FG