TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 536

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

15.4
Operations
15.4
15.4.1
15.4.2
15.4.2.1
Operations
Event counters.
CEC lines are sampled by a 32.768kHz of low speed clock (fs) or TBxOUT which is output of 16bit Timer/
The sampling clock is configurable with the <CECCLKC> bits of the CECFSSEL register.
STAT<CECRISTA> is set. The start bit interrupt is generated when the CECRCR3<CECRSTA> is set to
"1".
and a received interruption generates. By generating the received interruption, CECRSTAT<CE-
CRIEND> is set.
in the CEC circuit internally. This bit is generated from a observation of CEC signal same as other data.
with EOM bit set to"1". Detecting the end of last block, CEC becomes the start bit waiting mode.
The received data is discarded.
Sampling clock
Reception
If a start bit is detected, a start bit interruption generates. By generating start bit interruption, CECR-
If one byte data, EOM bit and ACK bit are received, the received data is stored in CECRBUF register,
In the CECRBUF register, 8 bit data, EOM bit and ACK bit are stored. The ACK bit is not generated
After one data block is received, receiving operation continues until detecting the last block of data
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start bit.
Note:Regarding data reception, please carefully read "15.1.3 Precautions".
interrupt
Start bit
Basic Operation
S
H
D1
D2
D3
Page 510
D4
Receiving interrupt
Dn-2
Dn-1
TMPM364F10FG
Dn