P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 100

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
The correspondence between boundary-scan cells and system pins, system direction controls and system
output enables is as shown in Table 25: Boundary Scan Signals & Pins . The cells are listed in the order in
which they are connected in the boundary-scan register, starting with the cell closest to TDI . All boundary-
scan register cells at input pins can apply tests to the on-chip core logic.
The EXTEST guard values specified in Table 25: Boundary Scan Signals & Pins should be clocked into the
boundary-scan register (using the SAMPLE/PRELOAD instruction) before the EXTEST instruction is
selected, to ensure that known data is applied to the core logic during the test. The INTEST guard values
shown in the table below should be clocked into the boundary-scan register (using the SAMPLE/
PRELOAD instruction) before the INTEST instruction is selected to ensure that all outputs are disabled.
These guard values should also be used when new EXTEST or INTEST vectors are clocked into the
boundary-scan register.
The values stored in the BS register after power-up are not defined. Similarly, the values previously clocked
into the BS register are not guaranteed to be maintained across a Boundary Scan reset (from forcing nTRST
LOW or entering the Test Logic Reset state).
8.6.4 Output Enable Boundary-scan Cells
The boundary-scan register cells Nendout, Nabe, Ntbe, and Nmse control the output drivers of tristate
outputs as shown in the table 25. In the case of OUTEN0 enable cells (Nendout, Ntbe), loading a 1 into the
cell will place the associated drivers into the tristate state, while in the case of type INEN1 enable cells
(Nabe, Nmse), loading a 0 into the cell will tristate the associated drivers.
To put all ARM60 tristate outputs into their high impedance state, a logic 1 should be clocked into the
output enable boundary-scan cells Nendout and Ntbe, and a logic 0 should be clocked into Nabe and Nmse.
Alternatively, the HIGHZ instruction can be used.
If the on-chip core logic causes the drivers controlled by Nendout, for example, to be tristate, (i.e. by driving
the signal Nendout HIGH), then a 1 will be observed on this cell if the SAMPLE/PRELOAD or INTEST
instructions are active.
8.6.5 Single-step Operation
ARM60 is a static design and there is no minimum clock speed. It can therefore be single-stepped while the
INTEST instruction is selected. This can be achieved by serialising a parallel stimulus and clocking the
resulting serial vectors into the boundary-scan register. When the boundary-scan register is updated, new
test stimuli are applied to the core logic inputs; the effect of these stimuli can then be observed on the core
logic outputs by capturing them in the boundary-scan register.
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