P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 69

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

5.0 Memory Interface
ARM60 communicates with its memory system via a bidirectional data bus ( D[31:0] ). A separate 32 bit
address bus specifies the memory location to be used for the transfer, and the nRW signal gives the
direction of transfer (ARM60 to memory or memory to ARM60). Control signals give additional
information about the transfer cycle, and in particular they facilitate the use of DRAM page mode where
applicable. Interfaces to static RAM based memories can also be interfaced to and, in general, they are much
simpler than the DRAM interface described here.
5.1 Cycle types
All memory transfer cycles can be placed in one of four categories:
(1)
(2)
(3)
(4)
These four classes are distinguishable to the memory system by inspection of the nMREQ and SEQ control
lines (see Table 6: Memory Cycle Types ). These control lines are generated during phase 1 of the cycle before
the cycle whose characteristics they forecast, and this pipelining of the control information gives the
memory system sufficient time to decide whether or not it can use a page mode access.
Figure 29: ARM Memory Cycle Timing shows the pipelining of the control signals, and suggests how the
DRAM address strobes ( nRAS and nCAS ) might be timed to use page mode for S-cycles. Note that the N-
cycle is longer than the other cycles. This is to allow for the DRAM precharge and row access time, and is
not an ARM60 requirement.
Non-sequential cycle. ARM60 requests a transfer to or from an address which is unrelated to the
address used in the preceding cycle.
Sequential cycle. ARM60 requests a transfer to or from an address which is either the same as the
address in the preceding cycle, or is one word after the preceding address.
Internal cycle. ARM60 does not require a transfer, as it is performing an internal function and no
useful prefetching can be performed at the same time.
Coprocessor register transfer. ARM60 wishes to use the data bus to communicate with a
coprocessor, but does not require any action by the memory system.
nMREQ
0
0
1
1
SEQ
0
1
0
1
Table 6: Memory Cycle Types
Non-sequential cycle
Sequential cycle
Internal cycle
Coprocessor register transfer
Cycle type
Memory Interface
(N-cycle)
(C-cycle)
(S-cycle)
(I-cycle)
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