P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 102

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
98
Tbscl
Tbsch
Tbsis
Tbsih
Tbsod
Tbsoh
Tbsoe
Tbsoz
Tbsss
Tbssh
Tbsdd
Tbsdh
Tbsde
Tbsdz
Tbsr
Tbsrs
Tbsrh
TCK may be stopped indefinitely in either the low or high phase.
Assumes a 25pF load on TDO. Output timing derates at 0.072ns/pF of extra load applied.
TDO enable time applies when the TAP controller enters the Shift-DR or Shift-IR states.
TDO disable time applies when the TAP controller leaves the Shift-DR or Shift-IR states.
For correct data latching, the I/O signals (from the core and the pads) must be setup and held with
respect to the rising edge of TCK in the CAPTURE-DR state of the SAMPLE/PRELOAD, INTEST
and EXTEST instructions.
Assumes that the data outputs are loaded with the AC test loads (see AC parameter specification).
Data output enable time applies when the boundary scan logic is used to enable the output drivers.
Data output disable time applies when the boundary scan is used to disable the output drivers.
TMS must be held high as nTRST is taken high at the end of the boundary-scan reset sequence.
Symbol
TCK low period
TCK high period
TDI,TMS setup to [TCr]
TDI,TMS hold from [TCr]
TCf to TDO valid
TDO hold time
TDO enable time
TDO disable time
I/O signal setup to [TCr]
I/O signal hold from [TCr]
TCf to data output valid
data output hold time
data output enable time
data output disable time
Reset period
tms setup to [TRr]
tms hold from [TRr]
Table 24: ARM60 Boundary Scan Interface Timing
Parameter
Min
48
48
10
10
10
15
20
10
10
3
3
5
5
Typ
Max
40
40
30
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2,4
6,8
2,3
6,7
1
1
2
5
2
5
6
9
9